 |
Electronic Components Datasheet Search |
|
|
Electronic Components Datasheet Search |
|
ADS8699IPWR Datasheet(PDF) 10 Page - Texas Instruments |
|
|
|||||||||||||||||||||||||||||
ADS8699IPWR Datasheet(HTML) 10 Page - Texas Instruments |
|
|
10 / 74 page  6.6 Timing Requirements: Conversion Cycle all minimum and maximum specifications are at TA = –40°C to +125°C; typical specifications are at TA = 25°C; AVDD = 5 V, DVDD = 3.3 V, VREF = 4.096 V (internal), and maximum throughput (unless otherwise noted) MIN TYP MAX UNIT TIMING REQUIREMENTS fcycle Sampling frequency ADS8691 1000 kSPS ADS8695 500 ADS8699 100 tcycle ADC cycle time period 1/fcycle tacq Acquisition time ADS8691 335 ns ADS8695 1000 ADS8699 5000 TIMING SPECIFICATIONS tconv Conversion time ADS8691 665 ns ADS8695 1000 ADS8699 5000 6.7 Timing Requirements: Asynchronous Reset all minimum and maximum specifications are at TA = –40°C to +125°C; typical specifications are at TA = 25°C; AVDD = 5 V, DVDD = 3.3 V, VREF = 4.096 V (internal), and maximum throughput (unless otherwise noted) MIN TYP MAX UNIT TIMING REQUIREMENTS twl_RST Pulse duration: RST high 100 ns TIMING SPECIFICATIONS tD_RST_POR Delay time for POR reset: RST rising to RVS rising 20 ms tD_RST_APP Delay time for application reset: RST rising to CONVST/CS rising 1 µs tNAP_WKUP Wake-up time: NAP mode 20 µs tPWRUP Power-up time: PD mode 20 ms 6.8 Timing Requirements: SPI-Compatible Serial Interface all minimum and maximum specifications are at TA = –40°C to +125°C; typical specifications are at TA = 25°C; AVDD = 5 V, DVDD = 3.3 V, VREF = 4.096 V (internal), and maximum throughput (unless otherwise noted) MIN TYP MAX UNIT TIMING REQUIREMENTS fCLK Serial clock frequency 66.67 MHz tCLK Serial clock time period 1/fCLK tPH_CK SCLK high time 0.45 0.55 tCLK tPL_CK SCLK low time 0.45 0.55 tCLK tSU_CSCK Setup time: CONVST/CS falling to first SCLK capture edge 7.5 ns tSU_CKDI Setup time: SDI data valid to SCLK capture edge 7.5 ns tHT_CKDI Hold time: SCLK capture edge to (previous) data valid on SDI 7.5 ns tHT_CKCS Delay time: last SCLK capture edge to CONVST/CS rising 7.5 ns TIMING SPECIFICATIONS tDEN_CSDO Delay time: CONVST/CS falling edge to data enable 9.5 ns tDZ_CSDO Delay time: CONVST/CS rising to SDO-x going to 3-state 10 ns tD_CKDO Delay time: SCLK launch edge to (next) data valid on SDO-x 12 ns tD_CSRVS Delay time: CONVST/CS rising edge to RVS falling 14 ns ADS8691, ADS8695, ADS8699 SBAS777B – DECEMBER 2016 – REVISED MARCH 2021 www.ti.com 10 Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: ADS8691 ADS8695 ADS8699 |
|
Link URL |
| Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Contact us | Privacy Policy | Link to Datasheet | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
English ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
