ADS8699IPWR datasheet(47/74 Pages) TI2

47 / 74 page

7.5.4.2.3 Source-Synchronous (SRC) Protocols

The multiSPI interface supports an ADC master clock or source-synchronous mode of data transfer between the

device and host controller. In this mode, the device provides an output clock that is synchronous with the output

data. Furthermore, the host controller can also select the output clock source and data bus width options in this

mode of operation. In all SRC modes of operation, the RVS pin provides the output clock, synchronous to the

device data output.

The SRC protocol allows the clock source (internal or external) and the width of the output bus to be configured,

similar to the SPI protocols.

7.5.4.2.3.1 Output Clock Source Options

The device allows the output clock on the RVS pin to be synchronous to either the external clock provided on the

SCLK pin or to the internal clock of the device. This selection is done by configuring the SSYNC_CLK bit, as

explained in the SDO_CTL_REG register. The timing diagram and specifications for operating the device with an

SRC protocol in external CLK mode are provided in Figure 6-7 and the Timing Requirements: Source-

Synchronous Serial Interface (External Clock) table. The timing diagram and specifications for operating the

device with an SRC protocol in internal CLK mode are provided in Figure 6-8 and the Timing Requirements:

Source-Synchronous Serial Interface (Internal Clock) table.

7.5.4.2.3.2 Output Bus Width Options

The device provides an option to increase the SDO-x bus width from one bit (default, single SDO-x) to two bits

(dual SDO-x) when operating with any of the SRC protocols. In order to operate the device in dual SDO mode,

the SDO1_CONFIG[1:0] bits in the SDO_CTL_REG register must be set to 11b. In this mode, the ALARM/

SDO-1/GPO pin functions as SDO-1.

Note

For any particular SRC protocol, the device follows the same timing specifications for single and dual

SDO modes. The only difference is that the device requires half as many clock cycles to output the

same number of bits when in single SDO mode, thus reducing the minimum required clock frequency

for a certain sampling rate of the ADC.

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ADS8691, ADS8695, ADS8699

SBAS777B – DECEMBER 2016 – REVISED MARCH 2021

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ADS8699IPWR Datasheet(PDF) 47 Page - Texas Instruments