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ADS8699IPWR Datasheet(PDF) 12 Page - Texas Instruments |
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ADS8699IPWR Datasheet(HTML) 12 Page - Texas Instruments |
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12 / 74 page ![]() 6.11 Timing Diagrams ADCST (Internal) tcycle RVS tconv tacq CONVST/CS The CS falling edge can be issued after tconv_max or when RVS goes high. Figure 6-1. Conversion Cycle Timing Diagram RVS twl_RST RST trst td_rst Figure 6-2. Asynchronous Reset Timing Diagram SCLK Data Read Time tSU_CSCK SDO-0 tDEN_CSDO tD_CKDO M M-1 M-2 L+1 L tD_CSDO tHT_CKCS SDI tSU_CKDI tHT_CKDI tconv_max tD_CSRVS RVS tcycle tD_CSRVS CPOL = 0 CPOL = 1 CONVST/CS Figure 6-3. Standard SPI Interface Timing Diagram for CPHA = 0 ADS8691, ADS8695, ADS8699 SBAS777B – DECEMBER 2016 – REVISED MARCH 2021 www.ti.com 12 Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: ADS8691 ADS8695 ADS8699 |
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