ADS8699IPWR datasheet(51/74 Pages) TI2

51 / 74 page

7.6.1.4 SDO_CTL_REG Register (address = 0Ch)

This register controls the data protocol used to transmit data out from the SDO-x pins of the device.

Figure 7-20. SDO_CTL_REG Register

Reserved

R-0000h

Reserved

GPO_VAL

Reserved

SDO1_

CONFIG

[1:0]

Reserved

SSYNC_CLK

Reserved

SDO_

MODE[1:0]

R-000b

R/W-0b

R-00b

R/W-00b

R-0b

R/W-<0>b

R-0h

R/W-<0>b

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset; -0, -1 = Condition after application reset;

LEGEND: -<0>, -<1> = Condition after power-on reset

Address for bits 7-0 = 0Ch

Address for bits 15-8 = 0Dh

Address for bits 23-16 = 0Eh

Address for bits 31-24 = 0Fh

Table 7-14. SDO_CTL_REG Register Field Descriptions

Bit

Field

Type

Reset

Description

31-16

Reserved

0000h

Reserved. Reads return 0h.

15-13

Reserved

000b

Reserved. Reads return 000b.

GPO_VAL

R/W

1-bit value for the output on the GPO pin.

11-10

Reserved

00b

Reserved. Reads return 00b.

9-8

SDO1_CONFIG[1:0]

R/W

00b

Two bits are used to configure ALARM/SDO-1/GPO:

00b = SDO-1 is always tri-stated; 1-bit SDO mode

01b = SDO-1 functions as ALARM; 1-bit SDO mode

10b = SDO-1 functions as GPO; 1-bit SDO mode

11b = SDO-1 combined with SDO-0 offers a 2-bit SDO mode

Reserved

Reserved. Reads return 0b.

SSYNC_CLK(1)

R/W

This bit controls the source of the clock selected for source-synchronous

transmission.

0b = External SCLK (no division)

1b = Internal clock (no division)

5-2

Reserved

0000b

Reserved. Reads return 0000b.

1-0

SDO_MODE[1:0]

R/W

00b

These bits control the data output modes of the device.

0xb = SDO mode follows the same SPI protocol as that used for SDI; see

the SDI_CTL_REG register

10b = Invalid configuration

11b = SDO mode follows the ADC master clock or source-synchronous

protocol

(1)

This bit takes effect only in the ADC master clock or source-synchronous mode of operation.

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ADS8691, ADS8695, ADS8699

SBAS777B – DECEMBER 2016 – REVISED MARCH 2021

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