ADS8699IPWR datasheet(63/74 Pages) TI2

63 / 74 page

10 Layout

10.1 Layout Guidelines

Figure 10-1 illustrates a PCB layout example for the ADS869x.

• Partition the PCB into analog and digital sections. Care must be taken to ensure that the analog signals are

kept away from the digital lines. This layout helps keep the analog input and reference input signals away

from the digital noise. In this layout example, the analog input and reference signals are routed on the lower

side of the board and the digital connections are routed on the top side of the board.

• Using a single dedicated ground plane is strongly encouraged.

• Power sources to the ADS869x must be clean and well-bypassed. Using a 1-μF, X7R-grade, 0603-size

ceramic capacitor with at least a 10-V rating in close proximity to the analog (AVDD) supply pins is

recommended. For decoupling the digital supply pin (DVDD), a 1-μF, X7R-grade, 0603-size ceramic capacitor

with at least a 10-V rating is recommended. Placing vias between the AVDD, DVDD pins and the bypass

capacitors must be avoided. All ground pins must be connected to the ground plane using short, low-

impedance paths.

• There are two decoupling capacitors used for the REFCAP pin. The first is a small, 1-μF, 0603-size ceramic

capacitor placed close to the device pins for decoupling the high-frequency signals and the second is a

10-μF, 0805-size ceramic capacitor to provide the charge required by the reference circuit of the device. A

capacitor with an ESR less than 0.2 Ω is recommended for the 10-μF capacitor. Both of these capacitors

must be directly connected to the device pins without any vias between the pins and capacitors.

• The REFIO pin also must be decoupled with a minimum of 4.7-μF ceramic capacitor if the internal reference

of the device is used. The capacitor must be placed close to the device pins.

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ADS8691, ADS8695, ADS8699

SBAS777B – DECEMBER 2016 – REVISED MARCH 2021

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ADS8699IPWR Datasheet(PDF) 63 Page - Texas Instruments