ADS8699IPWR datasheet(34/74 Pages) TI2

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ADC Output

Input Alarm Threshold

+/-

Hysteresis

Alarm Flag Read

Input Active Alarm Flag

Input Tripped Alarm Flag

Other Input Alarm

SDO

ALARM

ADC

ADCST Rising

(End of Conversion)

AVDD Low Alarm

AVDD High Alarm

Figure 7-16. Alarm Functionality Schematic

7.3.9.1 Input Alarm

The device features a high and a low alarm on the analog input. The alarms corresponding to the input signal

have independently-programmable thresholds and a common hysteresis setting that can be controlled through

the ALARM_H_TH_REG and ALARM_L_TH_REG registers.

The device sets the input high alarm when the digital output exceeds the high alarm upper limit [high alarm

threshold (T)]. The alarm resets when the digital output is less than or equal to the high alarm lower limit [high

alarm (T) – H – 1). This function is shown in Figure 7-17.

Similarly, the input low alarm is triggered when the digital output falls below the low alarm lower limit [low alarm

threshold (T)]. The alarm resets when the digital output is greater than or equal to the low alarm higher limit [low

alarm (T) + H + 1]. This function is shown in Figure 7-18.

ADC Output

H_ALARM On

H_ALARM Off

(T ± H ± 1)

(T)

Figure 7-17. High ALARM Hysteresis

ADC Output

L_ALARM Off

L_ALARM On

(T + H + 1)

(T)

Figure 7-18. Low ALARM Hysteresis

7.3.9.2 AVDD Alarm

The device features a high and a low alarm on the analog voltage supply, AVDD. Unlike the input signal alarm,

the AVDD alarm has fixed trip points that are set by design. The device features an internal analog comparator

that constantly monitors the analog supply against the high and low threshold voltages. The high alarm is set if

AVDD exceeds a typical value of 5.3 V and the low alarm is asserted if AVDD drops below 4.7 V. This feature is

specially useful for debugging unusual device behavior caused by a glitch or brown-out condition on the analog

AVDD supply.

ADS8691, ADS8695, ADS8699

SBAS777B – DECEMBER 2016 – REVISED MARCH 2021

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