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ADS8699IPWR Datasheet(PDF) 49 Page - Texas Instruments |
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ADS8699IPWR Datasheet(HTML) 49 Page - Texas Instruments |
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49 / 74 page ![]() 7.6.1.2 RST_PWRCTL_REG Register (address = 04h) This register controls the reset and power-down features offered by the converter. Any write operation to the RST_PWRCTL_REG register must be preceded by a write operation with the register address set to 05h and the register data set to 69h. Figure 7-18. RST_PWRCTL_REG Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved R-0000h 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 WKEY[7:0] Reserved VDD_AL_ DIS IN_AL_DIS Reserved RSTn_APP NAP_EN PWRDN R/W-00h R-00b R/W-0b R/W-0b R-0b R/W-<0>b R/W-<0>b R/W-0b LEGEND: R/W = Read/Write; R = Read only; -n = value after reset; -0, -1 = Condition after application reset; LEGEND: -<0>, -<1> = Condition after power-on reset Address for bits 7-0 = 04h Address for bits 15-8 = 05h Address for bits 23-16 = 06h Address for bits 31-24 = 07h Table 7-12. RST_PWRCTL_REG Register Field Descriptions Bit Field Type Reset Description 31-16 Reserved R 0000h Reserved. Reads return 0000h. 15-8 WKEY[7:0] R/W 00h This value functions as a protection key to enable writes to bits 5-0. Bits are written only if WKEY is set to 69h first. 7-6 Reserved R 00b Reserved. Reads return 00b 5 VDD_AL_DIS R/W 0b 0b = VDD alarm is enabled 1b = VDD alarm is disabled 4 IN_AL_DIS R/W 0b 0b = Input alarm is enabled 1b = Input alarm is disabled 3 Reserved R 0b Reserved. Reads return 0h. 2 RSTn_APP(1) R/W 0b 0b = RST pin functions as a POR class reset (causes full device initialization) 1b = RST pin functions as an application reset (only user-programmed modes are cleared) 1 NAP_EN(2) R/W 0b 0b = Disables the NAP mode of the converter 1b = Enables the converter to enter NAP mode if CONVST/CS is held high after the current conversion completes 0 PWRDN(2) R/W 0b 0b = Puts the converter into active mode 1b = Puts the converter into power-down mode (1) Setting this bit forces the RST pin to function as an application reset until the next power cycle. (2) See the Electrical Characteristics table for details on the latency encountered when entering and exiting the associated low-power mode. www.ti.com ADS8691, ADS8695, ADS8699 SBAS777B – DECEMBER 2016 – REVISED MARCH 2021 Copyright © 2021 Texas Instruments Incorporated Submit Document Feedback 49 Product Folder Links: ADS8691 ADS8695 ADS8699 |
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