ADS8699IPWR datasheet(37/74 Pages) TI2

37 / 74 page

7.4.1.3 Multiple Devices: Daisy-Chain Topology

A typical connection diagram showing multiple devices in a daisy-chain topology is shown in Figure 7-22.

Device 1

Device 2

Device N

Host Controller

Figure 7-22. Daisy-Chain Connection Schematic

The CONVST/CS and SCLK inputs of all devices are connected together and controlled by a single

CONVST/CS and SCLK pin of the host controller, respectively. The SDI input pin of the first device in the chain

(device 1) is connected to the SDO-x pin of the host controller, the SDO-0 output pin of device 1 is connected to

the SDI input pin of device 2, and so forth. The SDO-0 output pin of the last device in the chain (device N) is

connected to the SDI pin of the host controller.

To operate multiple devices in a daisy-chain topology, the host controller must program the configuration

registers in each device with identical values. The devices must operate with a single SDO-0 output, using the

external clock with any of the legacy, SPI-compatible protocols for data read and data write operations. In the

SDO_CTL_REG register, bits 7-0 must be programmed to 00h.

All devices in the daisy-chain topology sample their analog input signals on the rising edge of the CONVST/CS

signal and the data transfer frame starts with a falling edge of the same signal. At the launch edge of the SCLK

signal, every device in the chain shifts out the MSB to the SDO-0 pin. On every SCLK capture edge, each device

in the chain shifts in data received on its SDI pin as the LSB bit of the unified shift register; see Figure 7-19.

Therefore, in a daisy-chain configuration, the host controller receives the data of device N, followed by the data

of device N-1, and so forth (in MSB-first fashion). On the rising edge of the CONVST/CS signal, each device

decodes the contents in its unified and takes appropriate action.

For N devices connected in a daisy-chain topology, an optimal data transfer frame must contain 32 × N SCLK

capture edges (see Figure 7-23). A shorter data transfer frame can result in an erroneous device configuration

and must be avoided. For a data transfer frame with > 32 × N SCLK capture edges, the host controller must

appropriately align the configuration data for each device before bringing CONVST/CS high.

The overall throughput of the system is proportionally reduced with the number of devices connected in a daisy-

chain topology.

www.ti.com

ADS8691, ADS8695, ADS8699

SBAS777B – DECEMBER 2016 – REVISED MARCH 2021

Submit Document Feedback

Product Folder Links: ADS8691 ADS8695 ADS8699

ADS8699IPWR Datasheet(PDF) 37 Page - Texas Instruments