ADS8699IPWR datasheet(44/74 Pages) TI2

44 / 74 page

7.5.4 Data Transfer Protocols

The device features a multiSPI interface that allows the host controller to operate at slower SCLK speeds and

still achieve the required cycle time with a faster response time.

• For any data write operation, the host controller can use any of the four legacy, SPI-compatible protocols to

configure the device, as described in the Protocols for Configuring the Device section.

• For any data read operation from the device, the multiSPI interface module offers the following options:

– Legacy, SPI-compatible protocol with a single SDO-x (see the Legacy, SPI-Compatible (SYS-xy-S)

Protocols with a Single SDO-x section)

– Legacy, SPI-compatible protocol with dual SDO-x (see the Legacy, SPI-Compatible (SYS-xy-S) Protocols

With Dual SDO-x section)

– ADC master clock or source-synchronous (SRC) protocol for data transfer (see the Source-Synchronous

(SRC) Protocols section)

7.5.4.1 Protocols for Configuring the Device

As described in Table 7-8, the host controller can use any of the four legacy, SPI-compatible protocols (SPI-00-

S, SPI-01-S, SPI-10-S, or SPI-11-S) to write data into the device.

Table 7-8. SPI Protocols for Configuring the Device

PROTOCOL

SCLK POLARITY

(At CS Falling Edge)

SCLK PHASE

(Capture Edge)

SDI_CTL_REG

SDO_CTL_REG

DIAGRAM

SPI-00-S

Low

Rising

00h

Figure 7-26

SPI-01-S

Low

Falling

01h

00h

Figure 7-26

SPI-10-S

High

Falling

02h

00h

Figure 7-27

SPI-11-S

High

Rising

03h

00h

Figure 7-27

On power-up or after coming out of any asynchronous reset, the device supports the SPI-00-S protocol for data

read and data write operations. To select a different SPI-compatible protocol, program the SDI_MODE[1:0] bits

in the SDI_CNTL_REG register. This first write operation must adhere to the SPI-00-S protocol. Any subsequent

data transfer frames must adhere to the newly-selected protocol. The SPI protocol selected by the configuration

of the SDI_MODE[1:0] is applicable to both read and write operations.

Figure 7-26 and Figure 7-27 detail the four protocols using an optimal data frame; see the Timing Requirements:

SPI-Compatible Serial Interface table for associated timing parameters.

Note

As explained in the Data Transfer Frame section, a valid write operation to the device requires a

minimum of 32 SCLKs to be provided within a data transfer frame.

SCLK

SDI

RVS

CPOL = 0

CPOL = 1

CONVST/CS

B31

B30

B29

Figure 7-26. Standard SPI Timing Protocol (CPHA =

0, 32 SCLK Cycles)

SCLK

SDI

RVS

CPOL = 0

CPOL = 1

CONVST/CS

B31

B30

Figure 7-27. Standard SPI Timing Protocol (CPHA =

1, 32 SCLK Cycles)

ADS8691, ADS8695, ADS8699

SBAS777B – DECEMBER 2016 – REVISED MARCH 2021

www.ti.com

Submit Document Feedback

Product Folder Links: ADS8691 ADS8695 ADS8699

ADS8699IPWR Datasheet(PDF) 44 Page - Texas Instruments

ADS8699IPWR Datasheet(HTML) 44 Page - Texas Instruments

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74

Datasheet Download

Link URL