R7F100LLL3CFB datasheet(46/148 Pages) RENESAS

46 / 148 page

RL78/L23

1. Outline

R01DS0502EJ0110 Rev.1.10

Page 46 of 145

Oct 31, 2025

Note 1. Overwrite the flash memory during operation at 2 MHz or a lower frequency.

Note 2. When the flash memory is to be overwritten, switch to high-speed main (HS) mode or low-speed main (LS) mode.

Note 3. The number of PWM outputs varies depending on the setting of channels in use (the number of masters and slaves). For

details, see 7.9.3 Operation for the multiple PWM output function in the RL78/L23 User’s Manual.

Note 4. This applies when the corresponding bit in the peripheral I/O redirection register (PIORx) is set to 1.

Note 5. In normal operation, executing the instruction code FFH triggers an internal reset, but this is not the case during emulation

by the on-chip debugging emulator.

Reset

• Reset by RESET pin

• Internal reset by watchdog timer

• Internal reset by power-on-reset

• Internal reset by voltage detectors (LVD0 and LVD1)

• Internal reset by illegal instruction executionNote 5

• Internal reset by RAM parity error

• Internal reset by illegal-memory access

Power-on-reset circuit

Detection voltage

• 1.50 V (typ.)

Voltage

detector

LVD0

Detection voltage

• Rising edge: 1.69 V to 3.96 V (6 stages)

• Falling edge: 1.65 V to 3.88 V (6 stages)

LVD1

Detection voltage

• Rising edge: 1.67 V to 4.16 V (18 stages)

• Falling edge: 1.63 V to 4.08 V (18 stages)

On-chip debugging

Available (tracing supported)

Power supply voltage

VDD = 1.6 to 5.5 V

Operating ambient temperature

TA = –40 to +105°C (3C: Industrial applications)

(4/4)

Item

44-pin

48-pin

52-pin

64-pin

80-pin

100-pin

R7F100LFx

R7F100LGx

R7F100LJx

R7F100LLx

R7F100LMx

R7F100LPx

R7F100LLL3CFB Datasheet(PDF) 46 Page - Renesas Technology Corp

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