R7F100LLL3CFB datasheet(99/148 Pages) RENESAS

99 / 148 page

RL78/L23

2. Electrical Characteristics

R01DS0502EJ0110 Rev.1.10

Page 99 of 145

Oct 31, 2025

8. In simplified SPI (CSI) communications in the master mode with devices operating at different voltage levels (1.8 V,

2.5 V, or 3 V) with the internal SCKp clock

Note

Use this rate with VDD ≥ Vb.

Caution

Select the TTL input buffer for the SIp pin, and the N-ch open-drain output (withstand voltage of VDD) mode for

the SOp and SCKp pins by using the port input mode register (PIMg) and port output mode register (POMg). For

VIH and VIL, see the DC characteristics with the TTL input buffer selected.

(Remarks are listed on page 102.)

(TA = -40 to +105°C, 1.8 V ≤ VDD ≤ 5.5 V, VSS = EVSS = 0 V)

(1/3)

Item

Symbols

Conditions

(high-speed main)

mode

(low-speed main)

mode

(low-power main)

mode

Unit

Min.

Max.

Min.

Max.

Min.

Max.

SCKp cycle time

tKCY1

tKCY1 ≥ 4/fCLK 4.0 V ≤ VDD ≤ 5.5 V,

2.7 V ≤ Vb ≤ 4.0 V,

Cb = 30 pF,

Rb = 1.4 kΩ

300

2300

2.7 V ≤ VDD < 4.0 V,

2.3 V ≤ Vb ≤ 2.7 V,

Cb = 30 pF,

Rb = 2.7 kΩ

500

2300

1.8 V ≤ VDD < 3.3 V,

1.6 V ≤ Vb ≤ 2.0 VNote,

Cb = 30 pF,

Rb = 5.5 kΩ

1150

2300

SCKp high-level width tKH1

4.0 V ≤ VDD ≤ 5.5 V,

2.7 V ≤ Vb ≤ 4.0 V,

Cb = 30 pF, Rb = 1.4 kΩ

tKCY1/2

-75

tKCY1/2

-75

tKCY1/2

-75

2.7 V ≤ VDD < 4.0 V,

2.3 V ≤ Vb ≤ 2.7 V,

Cb = 30 pF, Rb = 2.7 kΩ

tKCY1/2

-170

tKCY1/2

-170

tKCY1/2

-170

1.8 V ≤ VDD < 3.3 V,

1.6 V ≤ Vb ≤ 2.0 VNote,

Cb = 30 pF, Rb = 5.5 kΩ

tKCY1/2

-458

tKCY1/2

-458

tKCY1/2

-458

SCKp low-level width

tKL1

4.0 V ≤ VDD ≤ 5.5 V,

2.7 V ≤ Vb ≤ 4.0 V,

Cb = 30 pF, Rb = 1.4 kΩ

tKCY1/2

-12

tKCY1/2

-12

tKCY1/2

-50

2.7 V ≤ VDD < 4.0 V,

2.3 V ≤ Vb ≤ 2.7 V,

Cb = 30 pF, Rb = 2.7 kΩ

tKCY1/2

-18

tKCY1/2

-18

tKCY1/2

-50

1.8 V ≤ VDD < 3.3 V,

1.6 V ≤ Vb ≤ 2.0 VNote,

Cb = 30 pF, Rb = 5.5 kΩ

tKCY1/2

-50

tKCY1/2

-50

tKCY1/2

-50

R7F100LLL3CFB Datasheet(PDF) 99 Page - Renesas Technology Corp

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