R7F100LLL3CFB datasheet(101/148 Pages) RENESAS

101 / 148 page

RL78/L23

2. Electrical Characteristics

R01DS0502EJ0110 Rev.1.10

Page 101 of 145

Oct 31, 2025

8. In simplified SPI (CSI) communications in the master mode with devices operating at different voltage levels (1.8 V,

2.5 V, or 3 V) with the internal SCKp clock

Note 1.

This setting applies when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.

Note 2.

Use this value with VDD ≥ Vb.

Caution

Select the TTL input buffer for the SIp pin, and the N-ch open-drain output (withstand voltage of VDD) mode for

the SOp and SCKp pins by using the port input mode register (PIMg) and port output mode register (POMg). For

VIH and VIL, see the DC characteristics with the TTL input buffer selected.

(Remarks are listed on the next page.)

(TA = -40 to +105°C, 1.8 V ≤ VDD ≤ 5.5 V, VSS = EVSS = 0 V)

(3/3)

Item

Symbols

Conditions

(high-speed main)

mode

(low-speed main)

mode

(low-power main)

mode

Unit

Min.

Max.

Min.

Max.

Min.

Max.

SIp setup time to the

falling of SCKpNote 1

tSIK1

4.0 V ≤ VDD ≤ 5.5 V,

2.7 V ≤ Vb ≤ 4.0 V,

Cb = 30 pF, Rb = 1.4 kΩ

110

2.7 V ≤ VDD < 4.0 V,

2.3 V ≤ Vb ≤ 2.7 V,

Cb = 30 pF, Rb = 2.7 kΩ

110

1.8 V ≤ VDD < 3.3 V,

1.6 V ≤ Vb ≤ 2.0 VNote 2,

Cb = 30 pF, Rb = 5.5 kΩ

110

SIp hold time from the

falling of SCKpNote 1

tKSI1

4.0 V ≤ VDD ≤ 5.5 V,

2.7 V ≤ Vb ≤ 4.0 V,

Cb = 30 pF, Rb = 1.4 kΩ

2.7 V ≤ VDD < 4.0 V,

2.3 V ≤ Vb ≤ 2.7 V,

Cb = 30 pF, Rb = 2.7 kΩ

1.8 V ≤ VDD < 3.3 V,

1.6 V ≤ Vb ≤ 2.0 VNote 2,

Cb = 30 pF, Rb = 5.5 kΩ

Delay time from the

rising of SCKp to an

SOp outputNote 1

tKSO1

4.0 V ≤ VDD ≤ 5.5 V,

2.7 V ≤ Vb ≤ 4.0 V,

Cb = 30 pF, Rb = 1.4 kΩ

2.7 V ≤ VDD < 4.0 V,

2.3 V ≤ Vb ≤ 2.7 V,

Cb = 30 pF, Rb = 2.7 kΩ

1.8 V ≤ VDD < 3.3 V,

1.6 V ≤ Vb ≤ 2.0 VNote 2,

Cb = 30 pF, Rb = 5.5 kΩ

R7F100LLL3CFB Datasheet(PDF) 101 Page - Renesas Technology Corp

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