R7F100LLL3CFB datasheet(93/148 Pages) RENESAS

93 / 148 page

RL78/L23

2. Electrical Characteristics

R01DS0502EJ0110 Rev.1.10

Page 93 of 145

Oct 31, 2025

6. In UART communications with devices operating at different voltage levels (1.8 V, 2.5 V, 3 V)

Note 1.

Transfer rate in the SNOOZE mode is within the range from 4800 to 9600 bps.

Note 2.

The maximum operating frequencies of the CPU/peripheral hardware clock (fCLK) are:

Note 3.

Use this rate with EVDD0 ≥ Vb.

Caution

Select the TTL input buffer for the RxDq pin, and the N-ch open-drain output (withstand voltage of VDD) mode for

the TxDq pin by using the port input mode register (PIMg) and port output mode register (POMg). For VIH and VIL,

see the DC characteristics with the TTL input buffer selected.

Remark 1.

Vb[V]: Communication line voltage

Remark 2.

q: UART number (q = 0 to 3), g: PIM and POM number (g = 0 to 9, 12 to 14)

Remark 3.

fMCK: Serial array unit operation clock frequency

To set this operating clock, use the CKSmn bit in the serial mode register mn (SMRmn) (m: Unit number, n: Channel

number = 00 to 03, 10 to 13).

(TA = -40 to +105°C, 1.8 V ≤ VDD ≤ 5.5 V, VSS = EVSS = 0 V)

(1/2)

Item

Symbols

Conditions

(high-speed main)

mode

(low-speed main)

mode

(low-power main)

mode

Unit

Min.

Max.

Min.

Max.

Min.

Max.

Transfer

rate

Reception

4.0 V ≤ VDD ≤ 5.5 V,

2.7 V ≤ Vb ≤ 4.0 V

fMCK/6

Note 1

fMCK/6

Note 1

fMCK/6

Note 1

bps

Theoretical value of the

maximum transfer rate

fMCK = fCLKNote 2

5.3

0.33

Mbps

2.7 V ≤ VDD < 4.0 V,

2.3 V ≤ Vb ≤ 2.7 V

fMCK/6

Note 1

fMCK/6

Note 1

fMCK/6

Note 1

bps

Theoretical value of the

maximum transfer rate

fMCK = fCLKNote 2

5.3

0.33

Mbps

1.8 V ≤ VDD < 3.3 V,

1.6 V ≤ Vb ≤ 2.0 V

fMCK/6

Notes 1, 3

fMCK/6

Notes 1, 3

fMCK/6

Notes 1, 3

bps

Theoretical value of the

maximum transfer rate

fMCK = fCLKNote 2

5.3

0.33

Mbps

HS (high-speed main) mode : 32 MHz (1.8 V ≤ VDD ≤ 5.5 V)

4 MHz (1.6 V ≤ VDD ≤ 5.5 V)

LS (low-speed main) mode : 24 MHz (1.8 V ≤ VDD ≤ 5.5 V)

4 MHz (1.6 V ≤ VDD ≤ 5.5 V)

LP (low-power main) mode : 2 MHz (1.6 V ≤ VDD ≤ 5.5 V)

R7F100LLL3CFB Datasheet(PDF) 93 Page - Renesas Technology Corp

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