R7F100LLL3CFB datasheet(91/148 Pages) RENESAS

91 / 148 page

RL78/L23

2. Electrical Characteristics

R01DS0502EJ0110 Rev.1.10

Page 91 of 145

Oct 31, 2025

5. In simplified I2C communications with devices operating at same voltage levels

Note 1.

The listed times must be no greater than fMCK/4.

Note 2.

Set fMCK so that it will not exceed the hold time when SCLr is low or high.

Caution

Select the normal input buffer and N-ch open-drain output (withstand voltage of VDD) mode for the SDAr pin, and

normal output mode for the SCLr pin by using the port input mode register (PIMg) and port output mode register

(POMh).

(Remarks are listed on the next page.)

(TA = -40 to +105°C, 1.6 V ≤ VDD ≤ 5.5 V, VSS = EVSS = 0 V)

(2/2)

Item

Symbols

Conditions

(high-speed main)

mode

(low-speed main)

mode

(low-power main)

mode

Unit

Min.

Max.

Min.

Max.

Min.

Max.

Data setup time

(reception)

tSU:DAT

2.7 V ≤ VDD ≤ 5.5 V,

Cb = 50 pF, Rb = 2.7 kΩ

1/fMCK

+85

Note 2

1/fMCK

+85

Note 2

1/fMCK

+145

Note 2

1.8 V ≤ VDD ≤ 5.5 V,

Cb = 100 pF, Rb = 3 kΩ

1/fMCK

+145

Note 2

1/fMCK

+145

Note 2

1/fMCK

+145

Note 2

1.8 V ≤ VDD < 2.7 V,

Cb = 100 pF, Rb = 5 kΩ

1/fMCK

+230

Note 2

1/fMCK

+230

Note 2

1/fMCK

+230

Note 2

1.6 V ≤ VDD < 1.8 V,

Cb = 100 pF, Rb = 5 kΩ

1/fMCK

+290

Note 2

1/fMCK

+290

Note 2

1/fMCK

+290

Note 2

Data hold time

(transmission)

tHD:DAT

2.7 V ≤ VDD ≤ 5.5 V,

Cb = 50 pF, Rb = 2.7 kΩ

305

1.8 V ≤ VDD ≤ 5.5 V,

Cb = 100 pF, Rb = 3 kΩ

355

1.8 V ≤ VDD < 2.7 V,

Cb = 100 pF, Rb = 5 kΩ

405

1.6 V ≤ VDD < 1.8 V,

Cb = 100 pF, Rb = 5 kΩ

405

R7F100LLL3CFB Datasheet(PDF) 91 Page - Renesas Technology Corp

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