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R7F100LLL3CFB Datasheet(PDF) 98 Page - Renesas Technology Corp |
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R7F100LLL3CFB Datasheet(HTML) 98 Page - Renesas Technology Corp |
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98 / 148 page ![]() RL78/L23 2. Electrical Characteristics R01DS0502EJ0110 Rev.1.10 Page 98 of 145 Oct 31, 2025 7. In simplified SPI (CSI) communications in the master mode with devices operating at different voltage levels (2.5 V or 3 V) with the internal SCKp clock (the ratings below are only applicable to CSI00) Note 1. This setting applies when DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. Note 2. This setting applies when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0. Caution Select the TTL input buffer for the SIp pin, and the N-ch open-drain output (withstand voltage of VDD) mode for the SOp and SCKp pins by using the port input mode register (PIMg) and port output mode register (POMg). For VIH and VIL, see the DC characteristics with the TTL input buffer selected. Remark 1. Rb[Ω]: Communication line (SCKp, SOp) pull-up resistance, Cb[F]: Communication line (SCKp, SOp) load capacitance, Vb[V]: Communication line voltage Remark 2. p: CSI number (p = 00), g: PIM and POM number (g = 1), m: Unit number (m = 0), n: Channel number (n = 0) Remark 3. fMCK: Serial array unit operation clock frequency To set this operating clock, use the CKSmn bit in the serial mode register mn (SMRmn) (m: Unit number, n: Channel number = 00). Remark 4. The listed times are only valid when the peripheral I/O redirect function of CSI00 is not in use. (TA = -40 to +105°C, 2.7 V ≤ VDD ≤ 5.5 V, VSS = EVSS = 0 V) (2/2) Item Symbols Conditions HS (high-speed main) mode LS (low-speed main) mode LP (low-power main) mode Unit Min. Max. Min. Max. Min. Max. SIp setup time to the falling of SCKpNote 2 tSIK1 4.0 V ≤ VDD ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V, Cb = 20 pF, Rb = 1.4 kΩ 23 23 110 ns 2.7 V ≤ VDD < 4.0 V, 2.3 V ≤ Vb ≤ 2.7 V, Cb = 20 pF, Rb = 2.7 kΩ 33 33 110 ns SIp hold time from the falling of SCKpNote 2 tKSI1 4.0 V ≤ VDD ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V, Cb = 20 pF, Rb = 1.4 kΩ 10 10 10 ns 2.7 V ≤ VDD < 4.0 V, 2.3 V ≤ Vb ≤ 2.7 V, Cb = 20 pF, Rb = 2.7 kΩ 10 10 10 ns Delay time from the rising of SCKp to an SOp outputNote 2 tKSO1 4.0 V ≤ VDD ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V, Cb = 20 pF, Rb = 1.4 kΩ 10 10 10 ns 2.7 V ≤ VDD < 4.0 V, 2.3 V ≤ Vb ≤ 2.7 V, Cb = 20 pF, Rb = 2.7 kΩ 10 10 10 ns |
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