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R7F100LLL3CFB Datasheet(PDF) 97 Page - Renesas Technology Corp |
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R7F100LLL3CFB Datasheet(HTML) 97 Page - Renesas Technology Corp |
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97 / 148 page  RL78/L23 2. Electrical Characteristics R01DS0502EJ0110 Rev.1.10 Page 97 of 145 Oct 31, 2025 7. In simplified SPI (CSI) communications in the master mode with devices operating at different voltage levels (2.5 V or 3 V) with the internal SCKp clock (the ratings below are only applicable to CSI00) (Notes, Caution, and Remarks are listed on the next page.) (TA = -40 to +105°C, 2.7 V ≤ VDD ≤ 5.5 V, VSS = EVSS = 0 V) (1/2) Item Symbols Conditions HS (high-speed main) mode LS (low-speed main) mode LP (low-power main) mode Unit Min. Max. Min. Max. Min. Max. SCKp cycle time tKCY1 tKCY1 ≥ 2/fCLK 4.0 V ≤ VDD ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V, Cb = 20 pF, Rb = 1.4 kΩ 200 200 2300 ns 2.7 V ≤ VDD < 4.0 V, 2.3 V ≤ Vb ≤ 2.7 V, Cb = 20 pF, Rb = 2.7 kΩ 300 300 2300 ns SCKp high-level width tKH1 4.0 V ≤ VDD ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V, Cb = 20 pF, Rb = 1.4 kΩ tKCY1/2 -50 tKCY1/2 -50 tKCY1/2 -50 ns 2.7 V ≤ VDD < 4.0 V, 2.3 V ≤ Vb ≤ 2.7 V, Cb = 20 pF, Rb = 2.7 kΩ tKCY1/2 -120 tKCY1/2 -120 tKCY1/2 -120 ns SCKp low-level width tKL1 4.0 V ≤ VDD ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V, Cb = 20 pF, Rb = 1.4 kΩ tKCY1/2 -7 tKCY1/2 -7 tKCY1/2 -50 ns 2.7 V ≤ VDD < 4.0 V, 2.3 V ≤ Vb ≤ 2.7 V, Cb = 20 pF, Rb = 2.7 kΩ tKCY1/2 -10 tKCY1/2 -10 tKCY1/2 -50 ns SIp setup time to the rising of SCKp Note 1 tSIK1 4.0 V ≤ VDD ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V, Cb = 20 pF, Rb = 1.4 kΩ 58 58 479 ns 2.7 V ≤ VDD < 4.0 V, 2.3 V ≤ Vb ≤ 2.7 V, Cb = 20 pF, Rb = 2.7 kΩ 121 121 479 ns SIp hold time from the rising of SCKp Note 1 tKSI1 4.0 V ≤ VDD ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V, Cb = 20 pF, Rb = 1.4 kΩ 10 10 10 ns 2.7 V ≤ VDD < 4.0 V, 2.3 V ≤ Vb ≤ 2.7 V, Cb = 20 pF, Rb = 2.7 kΩ 10 10 10 ns Delay time from the falling of SCKp to an SOp output Note 1 tKSO1 4.0 V ≤ VDD ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V, Cb = 20 pF, Rb = 1.4 kΩ 60 60 60 ns 2.7 V ≤ VDD < 4.0 V, 2.3 V ≤ Vb ≤ 2.7 V, Cb = 20 pF, Rb = 2.7 kΩ 130 130 130 ns |
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