R7F100LLL3CFB datasheet(85/148 Pages) RENESAS

85 / 148 page

RL78/L23

2. Electrical Characteristics

R01DS0502EJ0110 Rev.1.10

Page 85 of 145

Oct 31, 2025

3. In simplified SPI (CSI) communications in the master mode with devices operating at same voltage levels with the

internal SCKp clock

Note 1.

This is for when the settings are DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. When the settings are DAPmn

= 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0, this is the setup time to or from the falling of SCKp.

Note 2.

This is for when the settings are DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. When the settings are DAPmn

= 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0, this is the delay time to the rising of SCKp.

Note 3.

C is the load capacitance of the SCKp and SOp output lines.

Caution

Select the normal input buffer for the SIp pin and the normal output mode for the SOp pin and SCKp pin by using

the port input mode register (PIMg) and the port output mode register (POMg).

Remark 1.

p: CSI number (p = 00, 01, 10, 11, 20, 21, 30, 31), g: PIM and POM number (g = 0 to 9, 12 to 14),

m: Unit number (m = 0, 1), n: Channel number (n = 0 to 3)

Remark 2.

fMCK: Serial array unit operation clock frequency

To set this operating clock, use the CKSmn bit in the serial mode register mn (SMRmn) (m: Unit number, n: Channel

number = 00 to 03, 10 to 13).

(TA = -40 to +105°C, 1.6 V ≤ VDD ≤ 5.5 V, VSS = EVSS = 0 V)

Item

Symbols

Conditions

(high-speed main)

mode

(low-speed main)

mode

(low-power main)

mode

Unit

Min.

Max.

Min.

Max.

Min.

Max.

SCKp cycle time

tKCY1

tKCY1 ≥ 4/fCLK 2.7 V ≤ VDD ≤ 5.5 V

125

166

2000

2.4 V ≤ VDD ≤ 5.5 V

250

2000

1.8 V ≤ VDD ≤ 5.5 V

500

2000

1.6 V ≤ VDD ≤ 5.5 V

1000

2000

SCKp

high-level width,

low-level width

tKH1,

tKL1

4.0 V ≤ VDD ≤ 5.5 V

tKCY1/2

-12

tKCY1/2

-21

tKCY1/2

-50

2.7 V ≤ VDD ≤ 5.5 V

tKCY1/2

-18

tKCY1/2

-25

tKCY1/2

-50

2.4 V ≤ VDD ≤ 5.5 V

tKCY1/2

-38

tKCY1/2

-38

tKCY1/2

-50

1.8 V ≤ VDD ≤ 5.5 V

tKCY1/2

-50

tKCY1/2

-50

tKCY1/2

-50

1.6 V ≤ VDD ≤ 5.5 V

tKCY1/2

-100

tKCY1/2

-100

tKCY1/2

-100

SIp setup time to

the rising of SCKp

Note 1

tSIK1

4.0 V ≤ VDD ≤ 5.5 V

110

2.7 V ≤ VDD ≤ 5.5 V

110

2.4 V ≤ VDD ≤ 5.5 V

110

1.8 V ≤ VDD ≤ 5.5 V

110

1.6 V ≤ VDD ≤ 5.5 V

220

SIp hold time from

the rising of SCKp

Note 1

tKSI1

1.6 V ≤ VDD ≤ 5.5 V

Delay time from

the falling of

SCKp to an SOp

outputNote 2

tKSO1

1.6 V ≤ VDD ≤ 5.5 V,

C = 30 pFNote 3

R7F100LLL3CFB Datasheet(PDF) 85 Page - Renesas Technology Corp

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