7643 datasheet(356/424 Pages) RENESAS

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7643 Group

REJ09B0133-0200

APPENDIX

3.3 Notes on use

Rev.2.00

Aug 28, 2006

page 33 of 98

3.3.8 Notes on timer

(1) Read/Write for timer

•The timer division ratio is : 1 / (n + 1)

(n = “0” to “255” written into the timer)

•When the value is loaded only in the latch, the value is loaded in the timer at the count pulse

following the count where the timer reaches “0016”.

•In the timers 1 to 3, switching of the count sources of timers 1 to 3 does not affect the values

of reload latches. However, that may make count operation started. Therefore, write values again

in the order of timers 1, 2 and then timer 3 after their count sources have been switched.

•The timer current count value can be read out by reading the timer.

(2) Pulse output

•When using the TOUT output of timer 1 or timer 2, set bit 1 of port P5 direction register to “1”

(output mode).

•The TOUT output pin is shared with the XCOUT pin. Accordingly, when using f(XCIN)/2 as the timer

1 count source (bit 2 of timer 123 mode register = “0”), XCOUT oscillation drive must be disabled

(bit 5 of clock control register = “1”) to input clocks from the XCIN pin.

•The P51/XCOUT/TOUT pin cannot function as an ordinary I/O port while XCIN-XCOUT is oscillating. When

XCIN-XCOUT oscillation is stopped or XCOUT oscillation drive is disabled, this can be used as the TOUT

output pin of timer 1 or 2.

(3) At STP instruction executed

When the STP instruction is executed or Reset occurs, the timer 1 is set to “FF16” and the internal

clock

φ divided by 8 is automatically selected as its count source. Additionally, the timer 2 is set

to “0116” and the timer 1’s output is automatically selected as its count source. When the STP

instruction is being executed, all bits except bit 4 of the timer 123 mode register (address 002916)

are initialized to “0”. It is not necessary to set T123M1 (timer 1 count stop bit) to “0” before

executing the STP instruction. After returning from Stop mode, reset the timer 1 (address 002416),

timer 2 (address 002516), and the timer 123 mode register (address 002916).

3.3.9 Notes on Stop mode

•When the STP instruction is executed, bit 7 of the clock control register (address 001F16) goes

to “0”. To return from stop mode, reset CCR7 to “1”.

•When using fSYN (set internal system clock select bit (CPMA6) to “1”) as the internal system clock,

switch CPMA6 to “0” before executing the STP instruction. Reset CPMA6 after the system

returns from Stop Mode and the frequency synthesizer has stabilized.

CPMA6 does not need to be switched to “0” when using the WIT instruction.

•When the STP instruction is executed or Reset occurs, the timer 1 is set to “FF16” and the internal

clock

φ divided by 8 is automatically selected as its count source. Additionally, the timer 2 is set

to “0116” and the timer 1’s output is automatically selected as its count source. When the STP

instruction is being executed, all bits except bit 4 of the timer 123 mode register (address 002916)

are initialized to “0”. It is not necessary to set T123M1 (timer 1 count stop bit) to “0” before

executing the STP instruction. After returning from Stop mode, reset the timer 1 (address 002416),

timer 2 (address 002516), and the timer 123 mode register (address 002916).

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