7643 datasheet(357/424 Pages) RENESAS

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7643 Group

REJ09B0133-0200

APPENDIX

3.3 Notes on use

Rev.2.00

Aug 28, 2006

page 34 of 98

3.3.10 Notes on reset

(1) Connecting capacitor

In case where the RESET signal rise time is long, connect a ceramic capacitor or others across

the RESET pin and the VSS pin. Use a 1000 pF or more capacitor for high frequency use. When

connecting the capacitor, note the following :

• Make the length of the wiring which is connected to a capacitor as short as possible.

• Be sure to verify the operation of application products on the user side.

q Reason

If the several nanosecond or several ten nanosecond impulse noise enters the RESET pin, it

may cause a microcomputer failure.

3.3.11 Notes on I/O port

(1) Notes in standby state

In standby state✽1 for low-power dissipation, do not make input levels of an I/O port “undefined”.

Pull-up (connect the port to VCC) or pull-down (connect the port to VSS) these ports through a resistor.

When determining a resistance value, note the following points:

• External circuit

• Variation of output levels during the ordinary operation

When using built-in pull-up resistor, note on varied current values:

• When setting as an input port : Fix its input level

• When setting as an output port : Prevent current from flowing out to external

q Reason

The potential which is input to the input buffer in a microcomputer is unstable in the state that

input levels of an I/O port are “undefined”. This may cause power source current.

✽1 standby state: stop mode by executing STP instruction

wait mode by executing WIT instruction

(2) Modifying output data with bit managing instruction

When the port latch of an I/O port is modified with the bit managing instruction✽2, the value of the

unspecified bit may be changed.

q Reason

The bit managing instructions are read-modify-write form instructions for reading and writing

data by a byte unit. Accordingly, when these instructions are executed on a bit of the port latch

of an I/O port, the following is executed to all bits of the port latch.

•As for bit which is set for input port:

The pin state is read in the CPU, and is written to this bit after bit managing.

•As for bit which is set for output port:

The bit value is read in the CPU, and is written to this bit after bit managing.

Note the following:

•Even when a port which is set as an output port is changed for an input port, its port latch holds

the output data.

•As for a bit of which is set for an input port, its value may be changed even when not specified

with a bit managing instruction in case where the pin state differs from its port latch contents.

✽2 Bit managing instructions: SEB and CLB instructions

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