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MCIMX503CVM8B Datasheet(PDF) 46 Page - Freescale Semiconductor, Inc

Part # MCIMX503CVM8B
Description  i.MX50 Applications Processors for Consumer Products
PDF  134 Pages
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Manufacturer  FREESCALE [Freescale Semiconductor, Inc]
Direct Link  http://www.freescale.com
Logo FREESCALE - Freescale Semiconductor, Inc

MCIMX503CVM8B Datasheet(HTML) 46 Page - Freescale Semiconductor, Inc

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i.MX50 Applications Processors for Consumer Products, Rev. 2
46
Freescale Semiconductor
Electrical Characteristics
4.5.8
LPDDR1 I/O AC Parameters
Table 33 shows the AC parameters for LPDDR1 I/O.
4.5.9
LPDDR2 I/O AC Parameters
Table 34 shows the AC parameters for LPDDR2 I/O.
Table 33. LPDDR1 I/O AC Parameters
Parameter
Symbol
Min
Max
Unit
AC input logic high
Vihd(ac)
0.8*ovdd
ovdd+0.3
V
AC input logic low
Vild(ac)
-0.3
0.2*ovdd
AC input differential voltage1
1Vid(ac) specifies the input differential voltage |Vtr-Vcp| required for switching, where Vtr is
the “true” input signal and Vcp is the “complementary” input signal. The Minimum value is
equal to Vih(ac)-Vil(ac)
Vid(ac)
0.6*ovdd
ovdd+0.6
AC input differential crosspoint voltage2
2The typical value of Vix(ac) is expected to be about 0.5*ovdd. and Vix(ac) is expected to
track variation of ovdd. Vix(ac) indicates the voltage at which differential input signal must
cross.
Vix(ac)
0.4*ovdd
0.6*ovdd
Output propagation delay high to low
tPOHLD
2.5
ns
Output propagation delay low to high
tPOLHD
2.5
Input propagation delay high to low
tPIHLD
1.5
Input propagation delay low to high
tPILHD
1.5
Single output slew rate
tsr
0.3
2.5
V/ns
Table 34. LPDDR2 I/O AC Parameters
Parameter
Symbol
Min
Max
Unit
AC input logic high
Vih(ac)
Vref+0.22
ovdd
V
AC input logic low
Vil(ac)
ovss
Vref-0.22
AC differential input high voltage1
Vidh(ac)
0.44
-
AC differential input low voltage
Vidhl(ac)
-
0.44
AC input differential cross point voltage (relative
to ovdd / 2)2
Vix(ac)
-0.12
0.12
Over/undershoot peak
Vpeak
0.35
ns
Over/undershoot area (above OVDD or below
OVSS)
Varea
0.6 (at 266
MHz)
V-ns
Output propagation delay high to low
tPOHLD
3.5
ns
Output propagation delay low to high
tPOLHD
3.5
Input propagation delay high to low
tPIHLD
1.5
Input propagation delay low to high
tPILHD
1.5



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