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MCIMX503CVM8B Datasheet(PDF) 49 Page - Freescale Semiconductor, Inc |
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MCIMX503CVM8B Datasheet(HTML) 49 Page - Freescale Semiconductor, Inc |
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49 / 134 page ![]() Electrical Characteristics i.MX50 Applications Processors for Consumer Products, Rev. 2 Freescale Semiconductor 49 4.6.5 General Purpose Media Interface (GPMI) Parameters The i.MX50 GPMI controller is a flexible interface NAND Flash controller with 8-bit data width, up to 200 MB/s I/O speed and individual chip select. It supports Asynchronous timing mode, Source Synchronous timing mode and Samsung Toggle timing mode separately described in the following paragraphs. 4.6.5.1 Asynchronous Mode AC Timing (ONFI 1.0 Compatible) Asynchronous mode AC timings are provided as multiplications of the clock cycle and fixed delay. The Maximum I/O speed of GPMI in Asynchronous mode is about 50 MB/s. Figure 8, Figure 9, Figure 10 and Figure 11 depict the relative timing between GPMI signals at the module level for different Frequency lock time4 (FOL mode or non-integer MF) —— — 398 Tdpdref Phase lock time — — — 100 µs Frequency jitter5 (peak value) — — 0.02 0.04 Tdck Phase jitter (peak value) FPL mode, integer and fractional MF — 2.0 3.5 ns Power dissipation fdck = 300 MHz @ avdd = 1.8 V, dvdd = 1.2 V fdck = 650 MHz @ avdd = 1.8 V, dvdd = 1.2 V — — 0.65 (avdd) 0.92 (dvdd) 1.98 (avdd) 1.8 (dvdd) mW 1 Device input range cannot exceed the electrical specifications of the CAMP, see Table 37. 2 The values specified here are internal to DPLL. Inside the DPLL, a 1 is added to the value specified by the user. Therefore, the user has to enter a value 1 less than the desired value at the inputs of DPLL for PDF and MFD. 3 The maximum total multiplication factor (MFI + MFN/MFD) allowed is 15. Therefore, if the MFI value is 15, MFN value must be zero. 4 T dpdref is the time period of the reference clock after predivider. According to the specification, the maximum lock time in FOL mode is 398 cycles of divided reference clock when DPLL starts after full reset. 5 T dck is the time period of the output clock, dpdck_2. Table 38. DPLL Electrical Parameters (continued) Parameter Test Conditions/Remarks Min Typ Max Unit |
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