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MCIMX503CVM8B Datasheet(PDF) 88 Page - Freescale Semiconductor, Inc |
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MCIMX503CVM8B Datasheet(HTML) 88 Page - Freescale Semiconductor, Inc |
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88 / 134 page ![]() i.MX50 Applications Processors for Consumer Products, Rev. 2 88 Freescale Semiconductor Electrical Characteristics 4.9.9 SSI Timing Parameters This section describes the timing parameters of the SSI module. The connectivity of the serial synchronous interfaces are summarized in Table 64. NOTE • The terms WL and BL used in the timing diagrams and tables refer to Word Length (WL) and Bit Length (BL). • The SSI timing diagrams use generic signal names wherein the names used in the MCIMX50 Applications Processor Reference Manual (MCIMX50RM) are channel specific signal names. For example, a channel clock referenced in the IOMUXC chapter as AUD3_TXC appears in the timing diagram as TXC. Table 64. AUDMUX Port Allocation Port Signal Nomenclature Type and Access AUDMUX port 1 SSI 1 Internal AUDMUX port 2 SSI 2 Internal AUDMUX port 3 AUD3 External— AUD3 I/O AUDMUX port 4 AUD4 External—EIM or CSPI1 I/O through IOMUX AUDMUX port 5 AUD5 External—EIM or SD1 I/O through IOMUX AUDMUX port 6 AUD6 External—EIM or DISP2 through IOMUX |
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