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MCIMX503CVM8B Datasheet(PDF) 69 Page - Freescale Semiconductor, Inc

Part # MCIMX503CVM8B
Description  i.MX50 Applications Processors for Consumer Products
PDF  134 Pages
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Manufacturer  FREESCALE [Freescale Semiconductor, Inc]
Direct Link  http://www.freescale.com
Logo FREESCALE - Freescale Semiconductor, Inc

MCIMX503CVM8B Datasheet(HTML) 69 Page - Freescale Semiconductor, Inc

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Electrical Characteristics
i.MX50 Applications Processors for Consumer Products, Rev. 2
Freescale Semiconductor
69
4.8.2
DRAM Command and Address Output Timing—LPDDR2
The following diagrams and tables specify the timings related to the address and command pins, which
interface LPDDR2 memory devices.
Table 45. EMI Command/Address AC Timing
ID
Description
Symbol
Min
Max
Unit
DDR1
CK cycle time
tCK
3.75
ns
DDR2
CK high level width
tCH
0.48 tCK
0.52 tCK
ns
DDR3
CK low level width
tCL
0.48 tCK
0.52 tCK
ns
DDR4
Control output setup time
tIS
0.5 tCK
- 0.3
—ns
DDR5
Control output hold time
tIH
0.5 tCK
- 0.3
—ns
DDR6
CK >= 200 MHz
Address output setup time
tIS
0.5 tCK
- 1.3
—ns
DDR7
CK >= 200 MHz
Address output hold time
tIH
0.5 tCK
- 1.3
—ns
DDR6
CK < 200 MHz
Address output setup time
tIS
1
ns
DDR7
CK < 200 MHz
Address output hold time
tIH
1
ns
Figure 29. DRAM Command/Address Output Timing—LPDDR2
DRAM_SDCLK
DRAM_SDCLK_B
DRAM_CS0
DRAM_A[9:0]
DDR1
DDR2
DDR3
DDR4
DDR5
rise
fall
DDR6
DDR7



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