S25FS256S datasheet(37/154 Pages) SPANSION

37 / 154 page

November 6, 2013 S25FS-S_00_04

S25FS-S Family

Da ta

Shee t

(Prelim i nar y )

Timing Specifications

6.1

Key to Switching Waveforms

Figure 6.1 Waveform Element Meanings

6.2

AC Test Conditions

Figure 6.2 Test Setup

Notes:

1. Input slew rate measured from input pulse min to max at VDD max. Example: (1.9V x 0.8) - (1.9V x 0.2) = 1.14V; 1.14V/1.25V/ns = 0.9 ns

rise or fall time.

2. AC characteristics tables assume clock and data signals have the same slew rate (slope).

Figure 6.3 Input, Output, and Timing Reference Levels

Input

Symbol

Output

Valid at logic high or low

High Impedance

Any change permitted

Logic high Logic low

High Impedance

Changing, state unknown Logic high Logic low

Valid at logic high or low

Table 6.1 AC Measurement Conditions

Symbol

Parameter

Min

Max

Unit

Load Capacitance

Input Pulse Voltage

0.2xVDD

0.8 VDD

Input Slew Rate

0.23

1.25

V/ns

Input Rise and Fall Times

0.9

Input Timing Ref Voltage

0.5 VDD

Output Timing Ref

Voltage

0.5 VDD

Device

Under

Test

VDD + 0.4V

0.7 x VDD

0.3 x VDD

- 0.5V

Timing Reference Level

0.5 x VDD

VDD - 0.2V

0.2V

Input Levels

Output Levels

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