S25FS256S datasheet(40/154 Pages) SPANSION

40 / 154 page

S25FS-S Family

S25FS-S_00_04 November 6, 2013

Data

Sheet

(Pre limin ar y)

Figure 6.8 Hardware Reset when Quad Mode and IO3 / Reset# are Enabled

6.4

SDR AC Characteristics

Notes:

1. Only applicable as a constraint for WRR or WRAR instruction when SRWD is set to a 1.

2. Full VDD range and CL=30 pF.

3. Full VDD range and CL=15 pF.

4. Output High-Z is defined as the point where data is no longer driven.

5. tCS and tDIS require additional time when the Reset feature and Quad Mode are enabled (CR2V[5]=1 and CR1V[1]=1).

IO3_RESET#

CS#

Reset Pulse

Prior access using IO3 for data

tRP

tRH

tRPH

tC S

tDIS

Table 6.4 AC Characteristics

Symbol

Parameter

Min

Typ

Max

Unit

FSCK, R

SCK Clock Frequency for READ and 4READ

instructions

MHz

FSCK, C

SCK Clock Frequency for FAST_READ,

4FAST_READ, and the following Dual and Quad

commands: QOR, 4QOR, DIOR, 4DIOR, QIOR,

4QIOR

133

MHz

FSCK, D

SCK Clock Frequency for the following DDR

commands: QIOR, 4QIOR

MHz

PSCK

SCK Clock Period

1/ FSCK

∞

tWH, tCH

Clock High Time

50% PSCK -5%

50% PSCK +5%

tWL, tCL

Clock Low Time

50% PSCK -5%

50% PSCK +5%

tCRT, tCLCH

Clock Rise Time (slew rate)

0.1

V/ns

tCFT, tCHCL

Clock Fall Time (slew rate)

0.1

V/ns

tCS

CS# High Time (Read Instructions)

CS# High Time (Read Instructions when Reset

feature and Quad Mode are both enabled)

CS# High Time (Program/Erase instructions)

20 (5)

tCSS

CS# Active Setup Time (relative to SCK)

tCSH

CS# Active Hold Time (relative to SCK)

tSU

Data in Setup Time

tHD

Data in Hold Time

Clock Low to Output Valid

8 (2)

6 (3)

tHO

Output Hold Time

tDIS

Output Disable Time (4)

Output Disable Time (when Reset feature and Quad

Mode are both enabled)

20 (5)

tWPS

WP# Setup Time (1)

tWPH

WP# Hold Time (1)

100

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