S25FS256S datasheet(95/154 Pages) SPANSION

95 / 154 page

November 6, 2013 S25FS-S_00_04

S25FS-S Family

Da ta

Shee t

(Prelim i nar y )

10.3.3

Read Configuration Register (RDCR 35h)

The Read Configuration Register (RDCR) command allows the volatile Configuration Register (CR1V)

contents to be read from SO. It is possible to read CR1V continuously by providing multiples of eight clock

cycles. The Configuration Register contents may be read at any time, even while a program, erase, or write

operation is in progress.

Figure 10.9 Read Configuration Register (RDCR) Command Sequence

In QPI Mode, Configuration Register 1 may be read via the Read Any Register command, see

Section 10.3.12, Read Any Register (RDAR 65h) on page 101

10.3.4

Write Registers (WRR 01h)

The Write Registers (WRR) command allows new values to be written to both the Status Register 1 and

Configuration Register 1. Before the Write Registers (WRR) command can be accepted by the device, a

Write Enable (WREN) command must be received. After the Write Enable (WREN) command has been

decoded successfully, the device will set the Write Enable Latch (WEL) in the Status Register to enable any

write operations.

The Write Registers (WRR) command is entered by shifting the instruction and the data bytes on SI. The

Status Register is one data byte in length.

The WRR operation first erases the register then programs the new value as a single operation. The Write

Registers (WRR) command will set the P_ERR or E_ERR bits if there is a failure in the WRR operation. See

Status Register 1 Volatile (SR1V) on page 61 for a description of the error bits. Any Status or Configuration

CS# must be driven to the logic high state after the eighth or sixteenth bit of data has been latched. If not, the

Write Registers (WRR) command is not executed. If CS# is driven high after the eighth cycle then only the

Status Register 1 is written; otherwise, after the sixteenth cycle both the Status and Configuration Registers

are written.

As soon as CS# is driven to the logic high state, the self-timed Write Registers (WRR) operation is initiated.

While the Write Registers (WRR) operation is in progress, the Status Register may still be read to check the

value of the Write-In Progress (WIP) bit. The Write-In Progress (WIP) bit is a 1 during the self-timed Write

Registers (WRR) operation, and is a 0 when it is completed. When the Write Registers (WRR) operation is

completed, the Write Enable Latch (WEL) is set to a 0. The maximum clock frequency for the WRR command

is 133 MHz.

This command is also supported in QPI Mode. In QPI Mode the instruction and data is shifted in on IO0-IO3,

two clock cycles per byte.

Figure 10.10 Write Registers (WRR) Command Sequence – 8-Data Bits

CS#

SCK

Phase

Instruction

Repeat Register Read

CS#

SCK

Phase

Instruction

Input Status Register 1

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