S25FS256S datasheet(68/154 Pages) SPANSION

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S25FS-S Family

S25FS-S_00_04 November 6, 2013

Data

Sheet

(Pre limin ar y)

8.6.4.2

Configuration Register 2 Volatile (CR2V)

Related Commands: Read Any Register (RDAR 65h), Write Any Register (WRAR 71h), 4BAM.

Address Length CR2V[7]: This bit controls the expected address length for all commands that require

address and are not fixed 3-byte only or 4-byte (32-bit) only address. See Table 10.1, S25FS-S Family

Command Set (sorted by function) on page 88 for command address length. This volatile Address Length

configuration bit enables the address length to be changed during normal operation. The 4-byte address

mode (4BAM) command directly sets this bit into 4-byte address mode.

QPI CR2V[6]: This bit controls the expected instruction width for all commands. This volatile QPI

configuration bit enables the device to enter and exit QPI Mode during normal operation. When this bit is set

to QPI Mode, the Quad bit is also set to Quad Mode (CR1V[1]=1). When this bit is cleared to legacy SPI

mode, the Quad bit is not affected.

IO3 Reset CR2V[5]: This bit controls the IO3 / RESET# signal behavior. This volatile IO3 Reset configuration

bit enables the use of IO3 as a RESET# input during normal operation.

Read Latency CR2V[3:0]: This bit controls the read latency (dummy cycle) delay in variable latency read

commands These volatile configuration bits enable the user to adjust the read latency during normal

operation to optimize the latency for different commands or, at different operating frequencies, as needed.

Table 8.21 Configuration Register 2 Volatile (CR2V)

Bits

Field Name

Function

Type

Default

State

Description

Address Length

Volatile

CR2NV

1 = 4 byte address.

0 = 3 byte address.

QPI

1 = Enabled - QPI (4-4-4) protocol in use.

0 = Disabled - Legacy SPI protocols in use, instruction is

always serial on SI.

IO3R_S

IO3 Reset

1 = Enabled - IO3 is used as RESET# input when CS# is

high or Quad Mode is disabled CR1V[1]=1.

0 = Disabled - IO3 has no alternate function, hardware

reset is disabled.

RFU

Reserved

Reserved for Future Use.

Read Latency

0 to 15 latency (dummy) cycles following read address

or continuous mode bits.

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