S25FS256S datasheet(42/154 Pages) SPANSION

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S25FS-S Family

S25FS-S_00_04 November 6, 2013

Data

Sheet

(Pre limin ar y)

Figure 6.13 WP# Input Timing

6.5

DDR AC Characteristics

Notes:

1. CL=15 pF.

2. Output slew rate is measured between 20% and 80% of VDD.

CS#

WP#

SCLK

Phase

WRR or WRAR Instruction

Input Data

tWPS

tWPH

Table 6.5 AC Characteristics 80 MHz Operation

Symbol

Parameter

Min

Typ

Max

Unit

FSCK, R

SCK Clock Frequency for DDR READ instruction

MHz

PSCK, R

SCK Clock Period for DDR READ instruction

12.5

∞

tcrt

Clock Rise Time (slew rate)

1.5

V/ns

tcft

Clock Fall Time (slew rate)

1.5

V/ns

tWH, tCH

Clock High Time

50% PSCK -5%

50% PSCK +5%

tWL, tCL

Clock Low Time

50% PSCK -5%

50% PSCK +5%

tCS

CS# High Time (Read Instructions)

CS# High Time (Read Instructions when Reset

feature is enabled)

tCSS

CS# Active Setup Time (relative to SCK)

tCSH

CS# Active Hold Time (relative to SCK)

tSU

IO in Setup Time

1.5

tHD

IO in Hold Time

1.5

Clock Low to Output Valid

1.5

6 (1)

tHO

Output Hold Time

1.5

tDIS

Output Disable Time

Output Disable Time (when Reset feature is

enabled)

tIHTU

Time uncertainty due to variation in VIH

130

tILTU

Time uncertainty due to variation in VIL

130

tIO_skew

First IO to last IO data valid time

400

tIORT

Output Rise Time given 1.8V swing and 2.0v/ns slew

1.5

tIOFT

Output Fall Time given 1.8V swing and 2.0v/ns slew

1.5

ΔTV

Clock to data valid jitter

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