S25FS256S datasheet(38/154 Pages) SPANSION

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S25FS-S Family

S25FS-S_00_04 November 6, 2013

Data

Sheet

(Pre limin ar y)

6.2.1

Capacitance Characteristics

Note:

1. Parameter values are not 100% tested. For more details, please refer to the IBIS models.

6.3

Reset

6.3.1

Power-On (Cold) Reset

The device executes a Power-On Reset (POR) process until a time delay of tPU has elapsed after the

moment that VDD rises above the minimum VDD threshold. See Figure 5.3 on page 35, Table 5.3 on page 34.

The device must not be selected (CS# to go high with VDD) during power-up (tPU), i.e. no commands may be

sent to the device until the end of tPU.

The IO3 / RESET# signal functions as the RESET# input when CS# is high for more than tCS time or when

Quad Mode is not enabled CR1V[1]=0.

RESET# is ignored during POR. If RESET# is low during POR and remains low through and beyond the end

of tPU, CS# must remain high until tRH after RESET# returns high. RESET# must return high for greater than

tRS before returning low to initiate a hardware reset.

Figure 6.4 Reset Low at the End of POR

Figure 6.5 Reset High at the End of POR

Figure 6.6 POR Followed by hardware reset

Table 6.2 Capacitance

Parameter

Test Conditions

Min

Max

Unit

CIN

Input Capacitance (applies to SCK, CS#, IO3/RESET#)

1 MHz

COUT

Output Capacitance (applies to All I/O)

1 MHz

VCC

RESET#

CS#

If RESET# is low at tPU end

CS# must be high at tPU end

tPU

tRH

VCC

RESET#

CS#

If RESET# is high at tPU end

CS# may stay high or go low at tPU end

tPU

VCC

RESET#

CS#

tRS

tPU

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