S25FS256S datasheet(98/154 Pages) SPANSION

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S25FS-S Family

S25FS-S_00_04 November 6, 2013

Data

Sheet

(Pre limin ar y)

10.3.6

Write Disable (WRDI 04h)

The Write Disable (WRDI) command clears the Write Enable Latch (WEL) bit of the Status Register 1

(SR1V[1]) to a 1.

The Write Enable Latch (WEL) bit may be cleared to a 0 by issuing the Write Disable (WRDI) command to

disable Page Program (PP), Sector Erase (SE), Bulk Erase (BE), Write Registers (WRR or WRAR), OTP

Program (OTPP), and other commands, that require WEL be set to 1 for execution. The WRDI command can

be used by the user to protect memory areas against inadvertent writes that can possibly corrupt the contents

of the memory. The WRDI command is ignored during an embedded operation while WIP bit =1.

CS# must be driven into the logic high state after the eighth bit of the instruction byte has been latched in on

SI. Without CS# being driven to the logic high state after the eighth bit of the instruction byte has been latched

in on SI, the write disable operation will not be executed.

Figure 10.15 Write Disable (WRDI) Command Sequence

This command is also supported in QPI Mode. In QPI Mode the instruction is shifted in on IO0-IO3, two clock

cycles per byte.

Figure 10.16 Write Disable (WRDI) Command Sequence QPI Mode

CS#

SCK

Phase

Instruction

CS#

SCLK

IO0

IO1

IO2

IO3

Phase

Instruction

S25FS256S Datasheet(PDF) 98 Page - SPANSION