S25FS256S datasheet(96/154 Pages) SPANSION

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S25FS-S Family

S25FS-S_00_04 November 6, 2013

Data

Sheet

(Pre limin ar y)

Figure 10.11 Write Registers (WRR) Command Sequence – 16-Data Bits

Figure 10.12 Write Registers (WRR) Command Sequence – 16-Data Bits QPI Mode

The Write Registers (WRR) command allows the user to change the values of the Block Protect (BP2, BP1,

and BP0) bits in either the non-volatile Status Register 1 or in the volatile Status Register 1, to define the size

of the area that is to be treated as read-only. The BPNV_O bit (CR1NV[3]) controls whether WRR writes the

non-volatile or volatile version of Status Register 1. When CR1NV[3]=0 WRR writes SR1NV[4:2]. When

CR1NV[3]=1 WRR writes SR1V[4:2].

The Write Registers (WRR) command also allows the user to set the Status Register Write Disable (SRWD)

bit to a 1 or a 0. The Status Register Write Disable (SRWD) bit and Write Protect (WP#) signal allow the BP

bits to be hardware protected.

When the Status Register Write Disable (SRWD) bit of the Status Register is a 0 (its initial delivery state), it is

possible to write to the Status Register provided that the Write Enable Latch (WEL) bit has previously been

set by a Write Enable (WREN) command, regardless of the whether Write Protect (WP#) signal is driven to

the logic high or logic low state.

When the Status Register Write Disable (SRWD) bit of the Status Register is set to a 1, two cases need to be

considered, depending on the state of Write Protect (WP#):

 If Write Protect (WP#) signal is driven to the logic high state, it is possible to write to the Status and

Configuration Registers provided that the Write Enable Latch (WEL) bit has previously been set to a 1 by

initiating a Write Enable (WREN) command.

 If Write Protect (WP#) signal is driven to the logic low state, it is not possible to write to the Status and

Configuration Registers even if the Write Enable Latch (WEL) bit has previously been set to a 1 by a Write

Enable (WREN) command. Attempts to write to the Status and Configuration Registers are rejected, not

accepted for execution, and no error indication is provided. As a consequence, all the data bytes in the

memory area that are protected by the Block Protect (BP2, BP1, BP0) bits of the Status Register, are also

hardware protected by WP#.

The WP# hardware protection can be provided:

 by setting the Status Register Write Disable (SRWD) bit after driving Write Protect (WP#) signal to the logic

low state;

 or by driving Write Protect (WP#) signal to the logic low state after setting the Status Register Write Disable

(SRWD) bit to a 1.

The only way to release the hardware protection is to pull the Write Protect (WP#) signal to the logic high

state. If WP# is permanently tied high, hardware protection of the BP bits can never be activated.

CS#

SCK

Phase

Instruction

Input Status Register 1

Input Configuration Register 1

CS#

SCLK

IO0

IO1

IO2

IO3

Phase

Instruct.

Input Status

Input Config

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