MT9072AB datasheet(150/275 Pages) ZARLINK

150 / 275 page

MT9072

Data Sheet

150

Zarlink Semiconductor Inc.

Bit

Name

Functional Description

15-11

CHANNUM

(00000)

Channel Number.These 5 bits determine the channel that is used for updating of the

ST-Bus Analyzer buffer.

10-8

not used.

7-6

STRNUM

(00000)

Stream Number. These 5 bits determine the streams that will be used as the source data

for the ST-Bus Analyzer buffer.

00: DSTi

01: DSTo

10: CSTi

11: CSTo

5STBUFEN

(0)

ST-BUS Analyser Buffer Enable. Setting this bit enables the ST-BUS Analyser Buffer

update. When the user reads the buffer (920-93F), this bit must be 0. Any reads of the

buffer while this bit is set does not ensure correct data being read.

4-2

FNUM

(2:0)

(000)

Framer Number 0 to 7

CHUP

(0)

Channel Update. If 0 the update of the memory is at frame rate for a given channel. The

channel selected for update is provided by the ChanNum bits of this register. If set the

complete frame (channels 0 to 32) are updated to the buffer.

0CONTSIN

(0)

Continuous Single. If set to 1 the ST-BUS Analyzer buffer is updated continuously. If set

to zero the buffer is updated once and stopped. An optional interrupt can be generated

once the buffer is full1.

1. The ST-BUS Analyser can be used in continuous acquisition mode without any problem (Register 901, bit 0 is set). If the

ST-BUS analyser is used in the single mode (Register 901, bit 0 is cleared) an interrupt generated cannot be cleared and

the MT9072 has to be reset.

Table 120 - Global Control1 Register (R/W Address 901) (T1)

Bit

Name

Functional Description

F3HM

(0)

Framer 3 HDLC Mask. This is the mask bit for the F3HVS status bit in the Interrupt Vector

remain inactive (zero). If this mask bit is zero, the corresponding Interrupt Vector status bit will

function normally.

F3EM

(0)

Framer 3 Elastic Mask. This is the mask bit for the F3EVS status bit in the Interrupt Vector

remain inactive (zero). If this mask bit is zero, the corresponding Interrupt Vector status bit will

function normally.

F3RM

(0)

Framer 3 Rx Line Mask. This is the mask bit for the F3RVS status bit in the Interrupt Vector

remain inactive (zero). If this mask bit is zero, the corresponding Interrupt Vector status bit will

function normally.

Table 121 - Interrupt Vector 1 Mask Register (Address 902) (T1)

MT9072AB Datasheet(PDF) 150 Page - Zarlink Semiconductor Inc

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