MT9072AB datasheet(154/275 Pages) ZARLINK

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MT9072

Data Sheet

154

Zarlink Semiconductor Inc.

Bit

Name

Functional Description

SLBK8

(0)

ST-BUS Loopback 8M All. If one, DSTo[0] is connected to DSTi[4], and DSTo[4] is connected to

DSTi[0]. This can be used in 8.192 Mbit/s or 2.048 Mbit/s mode. See Loopbacks section.

SLBK67

(0)

ST-BUS Loopback Framer 6 & 7. If one, DSTo[6] is connected to DSTi[7], and DSTo[7] is

connected to DSTi[6]. Used only in 2.048 Mb/s mode. See Loopback section for details.

SLBK45

(0)

ST-BUS Loopback Framer 4 & 5. If one, DSTo[4] is connected to DSTi[5], and DSTo[5] is

connected to DSTi[4]. Used only in 2.048 Mb/s mode. See Loopbacks section.

SLBK23

(0)

ST-BUS Loopback Framer 2 & 3. If one, DSTo[2] is connected to DSTi[3], and DSTo[3] is

connected to DSTi[2]. Used only in 2.048 Mb/s mode. See Loopbacks section.

SLBK01

(0)

ST-BUS Loopback Framer 0 & 1. If one, DSTo[0] is connected to DSTi[1], and DSTo[1] is

connected to DSTi[0]. Used only in 2.048 Mb/s mode. See Loopbacks section.

RLBK8

(0)

Remote Loopback 8 Framers. If one, TPOS[0]/TNEG[0] are connected to RPOS[4]/RNEG[4],

and TPOS[4]/TNEG[4] are connected to RPOS[0]/RNEG[0]. This is used especially for

8.192 Mbit/s mode but may also be used in 2.048 Mbit/s mode. See Loopbacks section.

RLBK67

(0)

Remote Loopback Framer 6 & 7. If one, TPOS[6]/TNEG[6] are connected to

RPOS[7]/RNEG[7], and TPOS[7]/TNEG[7] are connected to RPOS[6]/RNEG[6]. Used only in

2.048 Mb/s mode. See Loopbacks section.

RLBK45

(0)

Remote Loopback Framer 4 & 5. If one, TPOS[4]/TNEG[4] are connected to

RPOS[5]/RNEG[5], and TPOS[5]/TNEG[5] are connected to RPOS[4]/RNEG[4]. Used only in

2.048 Mb/s mode. See Loopbacks section.

RLBK23

(0)

Remote Loopback Framer 2 & 3. If one, TPOS[2]/TNEG[2] are connected to

RPOS[3]/RNEG[3], and TPOS[3]/TNEG[3] are connected to RPOS[2]/RNEG[2]. Used only in

2.048 Mb/s mode. See Loopbacks section.

RLBK01

(0)

Remote Loopback Framer 0 & 1. If one, TPOS[0]/TNEG[0] are connected to

RPOS[1]/RNEG[1], and TPOS[1]/TNEG[1] are connected to RPOS[0]/RNEG[0]. Used only in

2.048 Mb/s mode. See Loopbacks section.

5-0

not used

Table 123 - Framer Loopback Global Register(904) (T1)

Bit

Name

Functional Description

F3HVS

(0)

Framer 3 HDLC Vector Status. This bit if unmasked is set if any of the bits in the Interrupt HDLC

address 902.

F3EVS

(0)

Framer 3 Elastic Vector Status. This bit if unmasked is set if any of the bits in the Interrupt

Receive Elasitc store register(336) or Elastic store status for Framer 3 are set. This bit can be

masked and will remain low by the F3EM bit in address 902.

F3RVS

(0)

Framer 3 Rx Line Vector Status. This bit if unmasked is set if any of the bits in the Interrupt

Receive Line status register(335) for Framer 0 are set. This bit can be masked and will remain

low by the F3RM bit in address 902.

Table 124 - Interrupt Vector 1 Status Register (Address 910) (T1)

MT9072AB Datasheet(PDF) 154 Page - Zarlink Semiconductor Inc

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