MT9072AB datasheet(156/275 Pages) ZARLINK

156 / 275 page

MT9072

Data Sheet

156

Zarlink Semiconductor Inc.

Bit

Name

Functional Description

F7HVS

(0)

Framer 3 HDLC Vector Status. This bit if unmasked is set if any of the bits in the Interrupt HDLC

address 903.

F7EVS

(0)

Framer 7 Elastic Vector Status. This bit if unmasked is set if any of the bits in the Interrupt

HDLC register(736) or Elastic store status for Framer 7 are set. This bit can be masked and will

remain low by the F7EM bit in address 903.

F7RVS

(0)

Framer 7 Rx Line Vector Status. This bit if unmasked is set if any of the bits in the Interrupt

HDLC register(735) for Framer 7 are set. This bit can be masked and will remain low by the

F7RM bit in address 903 .

F7SVS

(0)

Framer 7 Sync Vector Status. This bit if unmasked is set if any of the bits in the Interrupt HDLC

address 903.

F6HVS

(0)

Framer 6 HDLC Vector Status. This bit if unmasked is set if any of the bits in the Interrupt HDLC

low by the F7HM bit in address 903.

F6EVS

(0)

Framer 6 Elastic Vector Status. This bit if unmasked is set if any of the bits in the Interrupt

Receive Elasitc store register(636) or Elastic store status for Framer 5 are set. This bit can be

masked and will remain low by the F5EM bit in address 903.

9F6RVS

(0)

Framer 6 Rx Line Vector Status. This bit if unmasked is set if any of the bits in the Interrupt

Receive Line status register(635) for Framer 6 are set. This bit can be masked and will remain low

by the F6RM bit in address 903.

8F6SVS

(0)

Framer 6 Sync Vector Status. This bit if unmasked is set if any of the bits in the Interrupt

Counter status register(634) for Framer 6 are set. This bit can be masked and will remain low by

the F6SM bit in address 903.

7F5HVS

(0)

Framer 3 HDLC Vector Status. This bit if unmasked is set if any of the bits in the Interrupt HDLC

low by the F7HM bit in address 903.

6F5EVS

(0)

Framer 5 Elastic Vector Status. This bit if unmasked is set if any of the bits in the Interrupt

Receive Elasitc store register(536) or Elastic store status for Framer 5 are set. This bit can be

masked and will remain low by the F5EM bit in address 903.

5F5RVS

(0)

Framer 5 Rx Line Vector Status. This bit if unmasked is set if any of the bits in the Interrupt

Receive Line status register(535) are Framer 5 are set. This bit can be masked and will remain

low by theF1RM bit in address 903.

4F5SVS

(0)

Framer 5 Sync Vector Status. This bit if unmasked is set if any of the bits in the Interrupt Sync

status register(534) for Framer 5 are set. This bit can be masked and will remain low by the

F1SM bit in address 903.

3F4HVS

(0)

Framer 4 HDLC Vector Status. This bit if unmasked is set if any of the bits in the HDLC status

bit in address 903.

Table 125 - Interrupt Vector 2 Status Register (Address 911) (T1)

MT9072AB Datasheet(PDF) 156 Page - Zarlink Semiconductor Inc

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