MT9072AB datasheet(155/275 Pages) ZARLINK

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MT9072

Data Sheet

155

Zarlink Semiconductor Inc.

F3SVS

(0)

Framer 3 Sync Vector Status. This bit if unmasked is set if any of the bits in the Interrupt Sync

status register(334) for Framer 3 are set. This bit can be masked and will remain low by the

F3SM bit in address 902.

F2HVS

(0)

Framer 2 HDLC Vector Status. This bit if unmasked is set if any of the bits in the Interrupt HDLC

low by the F2HM bit in address 902.

F2EVS

(0)

Framer 2 Elastic Vector Status. This bit if unmasked is set if any of the bits in the Interrupt

Receive Elastic status register(236) or Elastic store status for Framer 2 are set. This bit can be

masked and will remain low by the F2EM bit in address 902.

9F2RVS

(0)

Framer 2 Rx Line Vector Status. This bit if unmasked is set if any of the bits in the Interrupt

Receive Line status register(235) for Framer 2 are set. This bit can be masked and will remain

low by the F2RM bit in address 902.

F2SVS

(0)

Framer 2 Sync Vector Status. This bit if unmasked is set if any of the bits in the Interrupt

Counter status register(234) for Framer 2 are set. This bit can be masked and will remain low by

the F2SM bit in address 902.

7F1HVS

(0)

Framer 1 HDLC Vector Status. This bit if unmasked is set if any of the bits in the Interrupt HDLC

low by the F2HM bit in address 902.

F1EVS

(0)

Framer 1 Elastic Vector Status. This bit if unmasked is set if any of the bits in the Interrupt

Receive Elasitc store register(136) or Elastic store status for Framer 1 are set. This bit can be

masked and will remain low by the F1EM bit in address 902.

5F1RVS

(0)

Framer 1 Rx Line Vector Status. This bit if unmasked is set if any of the bits in the Interrupt

Receive Line status register(135) for Framer 1 are set. This bit can be masked and will remain

low by theF1RM bit in address 902.

F1SVS

(0)

Framer 1 Sync Vector Status. This bit if unmasked is set if any of the bits in the Interrupt Sync

status register(134) for Framer 3 are set. This bit can be masked and will remain low by the

F1SM bit in address 902.

3F0HVS

(0)

Framer 0 HDLC Vector Status. This bit if unmasked is set if any of the bits in the Interrupt HDLC

low by the F0HM bit in address 902.

F0EVS

(0)

Framer 0 Elastic Vector Status. This bit if unmasked is set if any of the bits in the Interrupt

Receive Elasitc store register(036) or Elastic store status for Framer 0 are set. This bit can be

masked and will remain low by the F0EM bit in address 902.

1F0RVS

(0)

Framer 0 Rx Line Vector Status. This bit if unmasked is set if any of the bits in the Interrupt

Receive Line status register(035) for Framer 0 are set. This bit can be masked and will remain

low by the F0RM bit in address 902.

F0SVS

(0)

Framer 0 Sync Vector Status. This bit if unmasked is set if any of the bits in the Interrupt Sync

status register(034) for Framer 0 are set. This bit can be masked and will remain low by the

F0SM bit in address 902.

Bit

Name

Functional Description

Table 124 - Interrupt Vector 1 Status Register (Address 910) (T1) (continued)

MT9072AB Datasheet(PDF) 155 Page - Zarlink Semiconductor Inc

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