MT9072AB datasheet(157/275 Pages) ZARLINK

157 / 275 page

MT9072

Data Sheet

157

Zarlink Semiconductor Inc.

2F4EVS

(0)

Framer 4 Elastic Vector Status. This bit if unmasked is set if any of the bits in the Interrupt

Receive Elasitc store register(436) or Elastic store status for Framer 4 are set. This bit can be

masked and will remain low by the F4EM bit in address 903.

1F4RVS

(0)

Framer 4 Rx Line Vector Status. This bit if unmasked is set if any of the bits in the Interrupt

Receive Line status register(435) for Framer 4 are set. This bit can be masked and will remain low

by the F4RM bit in address 903.

0F4SVS

(0)

Framer 4 Sync Vector Status. This bit if unmasked is set if any of the bits in the Interrupt Sync

status register(434) Framer 4 are set. This bit can be masked and will remain low by the F4SM bit

in address 903.

Bit

Name

Functional Description

15-3

ID15-3

ID Number. Contains 0100000001011.

2-0

ID2-0

(000)

These 3 bits make up a binary code which identify the revision of this device.

Table 126 - Identification Revision Code Data Register (Address 912) (T1)

Bit

Name

Functional Description

15-1

not used.

0STIS

(0)

ST-BUS Analyser Interrupt Status. This bit is set if the ST-BUS Analyser is filled up.

Table 127 - ST-BUS Analyzer Vector Status Register (Address 913) (T1)

Bit

Name

Functional Description

15-8

not used.

7-0

STAD

(7-0)

(0)

ST-BUS Analyser Data. This is the data for the ST-BUS analyser buffer. 920 is the first byte of the

data that is being "analyzed". The source of the data can be any ST-Bus stream from any Framer.

Table 128 - ST-BUS Analyser Data(Address 920-93F) (T1)

Bit

Name

Functional Description

Table 125 - Interrupt Vector 2 Status Register (Address 911) (T1)

MT9072AB Datasheet(PDF) 157 Page - Zarlink Semiconductor Inc

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