MT9072AB datasheet(146/275 Pages) ZARLINK

146 / 275 page

MT9072

Data Sheet

146

Zarlink Semiconductor Inc.

Bit

Name

Functional Description

15-11

not used.

ADREC

(0)

Address Recognition.When high, this bit will enable address recognition. This forces the

receiver to recognize only those packets having the unique address as programmed in the

Receive Address Recognition Registers or if the address is an All Call Address.

9RXEN

(0)

Receive Enable.When low this bit will disable the HDLC receiver. The receiver will disable

after the rest of the packet presently being received is finished. The receiver’s internal clock

is disabled.

When high the receiver will be immediately enabled (depending on the state of RXCEN

input) and will begin searching for flags, Go-aheads etc.

8TXEN

(0)

Transmit Enable.When low this bit will disable the HDLC transmitter. The transmitter will

disable after the completion of the packet presently being transmitted. The transmitter’s

internal clock is disabled.

When high the transmitter will be immediately enabled (depending on the state of the

TXCEN input) and will begin transmitting data, or go to a mark idle or interframe time fill

state.

7EOP

(0)

End of Packet When set this bit will indicate an end of packet byte to the transmitter, which

will transmit an FCS following this byte. This facilitates loading of multiple packets into TX

FIFO. Reset automatically after a write to the TX FIFO occurs.

6FA

(0)

Framer Abort.Forms a tag on the next byte written to the TX FIFO, and when set will

indicate to the transmitter that it should abort the packet in which that byte is being

transmitted. Reset automatically after a write to the TX FIFO.

5MI

(0)

Mark-Idle.When low, the transmitter will be in an idle state. When high it is in an interframe

time fill state. These two states will only occur when the TX FIFO is empty.

4CYCLE

(0)

Cycle.When high, this bit will cause the transmit byte count to cycle through the value

loaded into the Transmit Byte Count Register.

TCRCI

(0)

Transmit CRC Inhibit. When high, this bit will inhibit transmission of the CRC. That is, the

transmitter will not insert the computed CRC onto the bit stream after seeing the EOP tag

byte. This is used in V.120 terminal adaptation for synchronous protocol sensitive UI frames.

SEVEN

(0)

Seven.When high, this bit will enable seven bits of address recognition in the first address

byte. The received address byte must have bit 0 equal to 1 which indicates a single address

byte is being received.

1RXFRST

(0)

Rx Fifo Reset.When high, the RX FIFO will be reset. This causes the receiver to be

disabled until the next reception of a flag. The status register will identify the FIFO as being

empty. However, the actual bit values in the RX FIFO will not be reset.

0TXFRST

(0)

Transmit FIFO Reset When high, the TX FIFO will be reset. The Status Register will identify

the FIFO as being empty. This bit will be reset when data is written to the TX FIFO. However,

the actual bit values of data in the TX FIFO will not be reset.

Table 113 - HDLC Control 1(YF2) (T1)

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