MT9072AB datasheet(145/275 Pages) ZARLINK

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MT9072

Data Sheet

145

Zarlink Semiconductor Inc.

Bit

Name

Functional Description

15-11

not used.

Tx8KEN

(0)

Transmit 8 KHz Enable. If one, the pin RxMF transmits a positive 8 KHz frame pulse

synchronous with the serial data stream TPOS/TNEG. If zero, the pin RxMF transmits a

negative frame pulse synchronous with the multiframe boundary of data coming out of DSTo.

9RxDO

(0)

Receive DSTo All Ones. If one, the DSTo pin operates normally. If zero, all timeslots (0-31)

of DSTo are set to one.

TXMFSEL

(0)

Transmit Multiframe Select. This bit is used to select if the framer is used for application of

the TXMF pulse which sets the multiframe boundary for the T1 transmitters. A one will select

the framer for application of TXMF.

SPND

(0)

Suspend Interrupts. If zero, the IRQ output will be in a high-impedance state and all

interrupts will be ignored. If one, the IRQ output will function normally.

6INTA

(0)

Interrupt Acknowledge. All interrupt and latched status registers for a particular framer

may be cleared (without reading the interrupt status registers) by setting the INTA control bit

to zero. Interrupt status registers for a particular framer will be cleared (and not updated) as

long as INTA is low. The framers interrupt vector bits will remain at zero, therefore that

framer cannot toggle the IRQ pin.

5DSToEN

(0)

DSTo Enable. If zero, pin DSTo is tristate. If set, pin DSTo is enabled.

4CSToEN

(0)

CSTo Enable. If zero, pin CSTo is tristate. If set, pin CSTo is enabled.

3RxCO

(0)

Receive CSTo All Ones.If one, the CSTo pin operates normally. If zero all timeslots of CSTo

are set to one

CNTCLR

(0)

Counter Clear. When this bit is changed from zero to one, all non-latched status counters

(address Y15 to Y1A) are cleared. If zero, all non-latched status counters operate normally.

SAMPLE

(0)

One Second Sample. Setting this bit causes the latched error counters(Y28 to Y2C)

(change of frame alignment, loss of frame alignment, bpv errors, crc errors, severely errored

frame events and multiframes out of sync) to be updated on one second intervals coincident

with the one second timer (Y11).

0RST

(0)

Reset. When this bit is changed from zero to one, the selected framer (Y) will reset to its

default mode. The default mode will depend on the T1E0 bit(Global control0 bit 15). Any

write to his bit should be followed by 125 usec before initialization of per timeslot control etc.

See the Reset Operation section for the default settings.

Table 112 - Interrupt and I/O Control(YF1) (T1)

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