MT9072AB datasheet(144/275 Pages) ZARLINK

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MT9072

Data Sheet

144

Zarlink Semiconductor Inc.

17.1.9

Master Control Registers (YF1 to YF7) Bit Functions

Tables 116 to 122 describe the bit functions of each of the Master Control Registers in the MT9072 for T1 mode.

Each register is repeated for each of the 8 framers. Framer 0 is addressed with Y=0, Framer 1 with Y=1, Framer 2

with Y=2,... Framer 7 with Y=7 (where Y represents the 4 most significant address bits (MSB) A11 A10 A9 A8). In

addition, a simultaneous write to all 8 Framers is possible by setting the address A11 to 1 and A10 to A8 to 0. A (0),

(1) or (#) in the “Name” column of these tables indicates the state of the data bits after a hard reset (the RESET pin

is toggled from zero to one), or a software reset (the RST bit in control register address YF1 is toggled from one to

zero or toggling of RSTC in Global Control Register). The (#) indicates that a (0) or (1) is possible.

Bit

Name

Functional Description

15-10

not used.

9RPCI

(0)

Receive Per Channel Inversion. The data received from the incoming DS1 channel is

inverted before it emerges from DSTo if this bit is set for the channel.

8MPDR

(0)

Micro Port Data Receive. Setting this bit allows for the receive data for a given channel to

be replaced by data in the idle code(Y09). The idle code can be written by the micro port for

trunk conditioning applications.

MPST

Micro Port Signaling Transmit. Setting this bit allows for the transmit signaling for a given

channel to be replaced by the bits in the Per Channel Transmit signaling Registration-TD of

registers Y50-Y67. They can be written by the micro port for trunk conditioning applications.

6TPCI

(0)

Transmit Per Channel Inversion. When set high the data for this channel sourced from

DSTi is inverted before being transmit onto the equivalent DS1 channel.

5RTSL

(0)

Remote Timeslot Loopback. If one, the corresponding DS1 receive timeslot is looped to

the corresponding DS1 transmit timeslot. This received timeslot will also be present on

DSTo. If zero, the receive loopback is disabled.

4LTSL

(0)

Local Timeslot Loopback. If one, the corresponding transmit timeslot is looped to the

corresponding receive timeslot. This transmit timeslot will also be present on the transmit

DS1 stream. If zero, this loopback is disabled.

3TTST

(0)

Transmit Test. If one the Mu-law digital milliwatt (where control bit ADSEQ is one) or a PRBS

generator (215-1) (ADSEQ is zero) will be transmitted in the corresponding DS1 timeslot.

More than one timeslot may be activated at once. If zero, the test signal will not be connected

to the corresponding timeslot.

2RRST

(0)

Receive Test. If one, the Mu-law digital milliwatt (where control bit ADSEQ is one) will be

sent to the DSTo or a PRBS data (215-1) (if ADSEQ is zero) will be expected in the

corresponding PCM 24 timeslot. If zero, the PRBS detector will not be connected to the

corresponding timeslot.

1MPDT

(0)

Micro Port Data Transmit. Setting this bit allows for the transmit data for a given channel to

be replaced by the idle code(Y0A). The idle code can be written by the micro port for trunk

conditioning applications. Ensure that TTST and RTSL are off.

0CC

(0)

Clear Channel. When set high no robbed bit signaling is inserted in the equivalent transmit

DS1 channel. When set low robbed bit signaling is included in every 6th frame.

Table 111 - Per Channel Control Word(Y90-YA7) (T1)

MT9072AB Datasheet(PDF) 144 Page - Zarlink Semiconductor Inc

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