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MB95F613K Datasheet(PDF) 108 Page - Cypress Semiconductor

Part # MB95F613K
Description  F2MC-8FX CPU core
PDF  110 Pages
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Manufacturer  CYPRESS [Cypress Semiconductor]
Direct Link  http://www.cypress.com
Logo CYPRESS - Cypress Semiconductor

MB95F613K Datasheet(HTML) 108 Page - Cypress Semiconductor

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Document Number: 002-04698 Rev. *A
Page 108 of 110
PRELIMINARY
MB95610H Series
22. Major Changes
Spansion Publication Number: DS702–00017–0v02-E
.
NOTE: Please see “Document History” about later revised information.
Page
Section
Details
19
Pin Connection
•DBG pin
Revised details of “• DBG pin”.
•RST pin
Revised details of “• RST pin”.
20
• C pin
Corrected the following statement.
The decoupling capacitor for the VCC pin must have a capacitance
larger than CS.
The decoupling capacitor for the VCC pin must have a capacitance
equal to or larger than the capacitance of CS.
75
Electrical Characteristics
Recommended Operating Conditions
Revised remark *1.
The minimum value becomes 2.88 V when the low-voltage
detection reset is used or in on-chip debug mode.
The minimum power supply voltage becomes 2.88 V when a
product with the low-voltage detection reset is used or when the
on-chip debug mode is used.
Corrected the following statement in remark *2.
The decoupling capacitor for the VCC pin must have a capacitance
larger than CS.
The decoupling capacitor for the VCC pin must have a capacitance
equal to or larger than the capacitance of CS.
Revised the remark in “• DBG/RST/C pins connection diagram”.
77
DC Characteristics
Revised the remark of the parameter “Input leak current (Hi-Z
output leak current)”.
When pull-up resistance is disabled
When the internal pull-up resistor is disabled
Rename the parameter “Pull-up resistance” to “Internal pull-up
resistor”.
Revised the remark of the parameter “Internal pull-up resistor”.
When pull-up resistance is enabled
When the internal pull-up resistor is enabled
82
AC Characteristics
Clock Timing
Corrected the pin names of the parameter “Input clock rising time
and falling time”.
X0
 X0, X0A
X0, X1
 X0, X1, X0A, X1A



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