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TNETV1647GSTZWT Datasheet(PDF) 220 Page - Texas Instruments |
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TNETV1647GSTZWT Datasheet(HTML) 220 Page - Texas Instruments |
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220 / 236 page  TMS320DM6441 SPRS359E – SEPTEMBER 2006 – REVISED AUGUST 2010 www.ti.com 6.23 VLYNQ The DM6441 VLYNQ peripheral provides a high speed serial communications interface with the following features. • Low pin count • Scalable performance/support • Simple packet based transfer protocol for memory mapped access – Write request/data packet – Read request packet – Read response data packet – Interrupt request packet • Supports both symmetric and asymmetric operation – Tx pins on first device connect to Rx pins on second device and vice versa – Data pin widths are automatically detected after reset – Request packets, response packets, and flow control information are all multiplexed and sent across the same physical pins – Supports both host/peripheral and peer-to-peer communication • Simple block code packet formatting (8-b/10-b) • In band flow control – No extra pins needed – Allows receiver to momentarily throttle back transmitter when overflow is about to occur – Uses built in special code capability of block code to seamlessly interleave flow control information with user data – Allows system designer to balance cost of data buffering versus performance • Multiple outstanding transactions • Automatic packet formatting optimizations • Internal loop-back mode 6.23.1 VLYNQ Peripheral Register Description(s) Table 6-105. VLYNQ Registers HEX ADDRESS RANGE ACRONYM REGISTER NAME 0x01E0 1000 - Reserved 0x01E0 1004 CTRL VLYNQ Local Control Register 0x01E0 1008 STAT VLYNQ Local Status Register 0x01E0 100C INTPRI VLYNQ Local Interrupt Priority Vector Status/Clear Register 0x01E0 1010 INTSTATCLR VLYNQ Local Unmasked Interrupt Status/Clear Register 0x01E0 1014 INTPENDSET VLYNQ Local Interrupt Pending/Set Register 0x01E0 1018 INTPTR VLYNQ Local Interrupt Pointer Register 0x01E0 101C XAM VLYNQ Local Transmit Address Map Register 0x01E0 1020 RAMS1 VLYNQ Local Receive Address Map Size 1 Register 0x01E0 1024 RAMO1 VLYNQ Local Receive Address Map Offset 1 Register 0x01E0 1028 RAMS2 VLYNQ Local Receive Address Map Size 2 Register 0x01E0 102C RAMO2 VLYNQ Local Receive Address Map Offset 2 Register 0x01E0 1030 RAMS3 VLYNQ Local Receive Address Map Size 3 Register 0x01E0 1034 RAMO3 VLYNQ Local Receive Address Map Offset 3 Register 0x01E0 1038 RAMS4 VLYNQ Local Receive Address Map Size 4 Register 0x01E0 103C RAMO4 VLYNQ Local Receive Address Map Offset 4 Register 0x01E0 1040 CHIPVER VLYNQ Local Chip Version Register 220 Peripheral and Electrical Specifications Copyright © 2006–2010, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320DM6441 |
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