TMS320F28076PZP datasheet(44/192 Pages) TI

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7.9 System

7.9.1 Power Management

7.9.1.1 Internal 1.2-V VREG

The internal VREG is supplied by VDDIO and generates the 1.2 V required to power the VDD pins. Enable this

functionality by pulling the VREGENZ pin low to VSS. Although the internal VREG eliminates the need to use an

external power supply for VDD, decoupling capacitors are required on each VDD pin for VREG stability (see the

description of VDD in Section 6.2.1). Driving an external load with the internal VREG is not supported.

7.9.1.2 Power Sequencing

7.9.1.2.1 Signal Pin Requirements

Before powering the device, no voltage larger than 0.3 V above VDDIO can be applied to any digital pin, and no

voltage larger than 0.3 V above VDDA can be applied to any analog pin (including VREFHI).

7.9.1.2.2 VDDIO, VDDA, VDD3VFL, and VDDOSC Requirements

The 3.3-V supplies should be powered up together and kept within 0.3 V of each other during functional

operation.

7.9.1.2.3 VDD Requirements

When VREGENZ is tied to VSS, the VDD sequencing requirements are handled by the device.

When using an external source for VDD (VREGENZ tied to VDDIO), VDDOSC and VDD must be powered on and off

at the same time. VDDOSC should not be powered on when VDD is off. During the ramp, VDD should be kept no

more than 0.3 V above VDDIO.

For applications not powering VDDOSC and VDD at the same time, see the "INTOSC: VDDOSC Powered Without

VDD Can Cause INTOSC Frequency Drift" advisory in the TMS320F2807x MCUs Silicon Errata.

There is an internal 12.8-mA current source from VDD3VFL to VDD when the flash is active. When the flash is

active and the device is in a low-activity state (for example, a low-power mode), this internal current source can

cause VDD to rise to approximately 1.3 V . There will be zero current load to the external system VDD regulator

while in this condition. This is not an issue for most regulators; however, if the system voltage regulator requires

a minimum load for proper operation, then an external 82Ω resistor can be added to the board to ensure a

minimal current load on VDD. See the "Low-Power Modes: Power Down Flash or Maintain Minimum Device

Activity" advisory in the TMS320F2807x MCUs Silicon Errata.

7.9.1.2.4 Supply Ramp Rate

The supplies should ramp to full rail within 10 ms. Section 7.9.1.2.4.1 shows the supply ramp rate.

7.9.1.2.4.1 Supply Ramp Rate

MIN

MAX

UNIT

Supply ramp rate

VDDIO, VDD, VDDA, VDD3VFL, VDDOSC with respect to VSS

330

105

V/s

7.9.1.2.5 Supply Supervision

An internal power-on-reset (POR) circuit keeps the I/Os in a high-impedance state during power up. External

supply voltage supervisors (SVS) can be used to monitor the voltage on the 3.3-V and 1.2-V rails and drive XRS

low when supplies are outside operational specifications.

Note

If the supply voltage is held near the POR threshold, then the device may drive periodic resets onto

the XRS pin.

TMS320F28076, TMS320F28075

SPRS902J – OCTOBER 2014 – REVISED FEBRUARY 2021

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