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TMS320F28076PZP Datasheet(PDF) 67 Page - Texas Instruments |
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TMS320F28076PZP Datasheet(HTML) 67 Page - Texas Instruments |
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67 / 192 page  Section 7.9.8.3.5 shows the HALT mode timing requirements, Section 7.9.8.3.6 shows the switching characteristics, and Figure 7-19 shows the timing diagram for HALT mode. 7.9.8.3.5 HALT Mode Timing Requirements MIN MAX UNIT tw(WAKE-GPIO) Pulse duration, GPIO wake-up signal(1) toscst + 2tc(OSCCLK) cycles tw(WAKE-XRS) Pulse duration, XRS wake-up signal(1) toscst + 8tc(OSCCLK) cycles (1) For applications using X1/X2 for OSCCLK, the user must characterize their specific oscillator start-up time as it is dependent on circuit/ layout external to the device. See Section 7.9.3.4.2 for more information. For applications using INTOSC1 or INTOSC2 for OSCCLK, see Section 7.9.3.5 for toscst. Oscillator start-up time does not apply to applications using a single-ended crystal on the X1 pin, as it is powered externally to the device. 7.9.8.3.6 HALT Mode Switching Characteristics over recommended operating conditions (unless otherwise noted) PARAMETER MIN MAX UNIT td(IDLE-XCOS) Delay time, IDLE instruction executed to XCLKOUT stop 16tc(INTOSC1) cycles td(WAKE-HALT) Delay time, external wake signal end to CPU1 program execution resume cycles • Wakeup from flash – Flash module in active state 75tc(OSCCLK) • Wakeup from flash – Flash module in sleep state 17500tc(OSCCLK) (1) • Wakeup from RAM 75tc(OSCCLK) (1) This value is based on the flash power-up time, which is a function of the SYSCLK frequency, flash wait states (RWAIT), and FPAC1[PSLEEP]. For more information, see the Flash and OTP Power-Down Modes and Wakeup section of the TMS320F2807x Microcontrollers Technical Reference Manual . This value can be realized when SYSCLK is 120 MHz, RWAIT is 2, and FPAC1[PSLEEP] is 0x860. www.ti.com TMS320F28076, TMS320F28075 SPRS902J – OCTOBER 2014 – REVISED FEBRUARY 2021 Copyright © 2021 Texas Instruments Incorporated Submit Document Feedback 67 Product Folder Links: TMS320F28076 TMS320F28075 |
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