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TMS320F28076PZP Datasheet(PDF) 76 Page - Texas Instruments

Part # TMS320F28076PZP
Description  TMS320F2807x Microcontrollers
PDF  192 Pages
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Manufacturer  TI [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI - Texas Instruments

TMS320F28076PZP Datasheet(HTML) 76 Page - Texas Instruments

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7.9.9.3.2 Synchronous RAM
Section 7.9.9.3.2.1 shows the EMIF synchronous memory timing requirements. Section 7.9.9.3.2.2 shows the
EMIF synchronous memory switching characteristics. Figure 7-25 and Figure 7-26 show the synchronous
memory timing diagrams.
7.9.9.3.2.1 EMIF Synchronous Memory Timing Requirements
NO.
MIN
MAX
UNIT
19
tsu(EMIFDV-EM_CLKH)
Input setup time, read data valid on EMxD[y:0] before EMxCLK rising
2
ns
20
th(CLKH-DIV)
Input hold time, read data valid on EMxD[y:0] after EMxCLK rising
1.5
ns
7.9.9.3.2.2 EMIF Synchronous Memory Switching Characteristics
NO.
PARAMETER
MIN
MAX
UNIT
1
tc(CLK)
Cycle time, EMIF clock EMxCLK
10
ns
2
tw(CLK)
Pulse width, EMIF clock EMxCLK high or low
3
ns
3
td(CLKH-CSV)
Delay time, EMxCLK rising to EMxCS[y:2] valid
8
ns
4
toh(CLKH-CSIV)
Output hold time, EMxCLK rising to EMxCS[y:2] invalid
1
ns
5
td(CLKH-DQMV)
Delay time, EMxCLK rising to EMxDQM[y:0] valid
8
ns
6
toh(CLKH-DQMIV)
Output hold time, EMxCLK rising to EMxDQM[y:0] invalid
1
ns
7
td(CLKH-AV)
Delay time, EMxCLK rising to EMxA[y:0] and EMxBA[y:0] valid
8
ns
8
toh(CLKH-AIV)
Output hold time, EMxCLK rising to EMxA[y:0] and EMxBA[y:0] invalid
1
ns
9
td(CLKH-DV)
Delay time, EMxCLK rising to EMxD[y:0] valid
8
ns
10
toh(CLKH-DIV)
Output hold time, EMxCLK rising to EMxD[y:0] invalid
1
ns
11
td(CLKH-RASV)
Delay time, EMxCLK rising to EMxRAS valid
8
ns
12
toh(CLKH-RASIV)
Output hold time, EMxCLK rising to EMxRAS invalid
1
ns
13
td(CLKH-CASV)
Delay time, EMxCLK rising to EMxCAS valid
8
ns
14
toh(CLKH-CASIV)
Output hold time, EMxCLK rising to EMxCAS invalid
1
ns
15
td(CLKH-WEV)
Delay time, EMxCLK rising to EMxWE valid
8
ns
16
toh(CLKH-WEIV)
Output hold time, EMxCLK rising to EMxWE invalid
1
ns
17
td(CLKH-DHZ)
Delay time, EMxCLK rising to EMxD[y:0] tri-stated
8
ns
18
toh(CLKH-DLZ)
Output hold time, EMxCLK rising to EMxD[y:0] driving
1
ns
TMS320F28076, TMS320F28075
SPRS902J – OCTOBER 2014 – REVISED FEBRUARY 2021
www.ti.com
76
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Copyright © 2021 Texas Instruments Incorporated
Product Folder Links: TMS320F28076 TMS320F28075



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