TMS320F28076PZP datasheet(23/192 Pages) TI

23 / 192 page

TERMINAL

I/O/Z

(1)

DESCRIPTION

NAME

MUX

POSITION

PTP

NO.

PZP

NO.

JTAG

TCK

JTAG test clock with internal pullup (see Section 7.6)

TDI

JTAG test data input (TDI) with internal pullup. TDI is clocked

into the selected register (instruction or data) on a rising edge

of TCK.

TDO

O/Z

JTAG scan out, test data output (TDO). The contents of the

selected register (instruction or data) are shifted out of TDO

on the falling edge of TCK.

(3)

TMS

JTAG test-mode select (TMS) with internal pullup. This serial

control input is clocked into the TAP controller on the rising

edge of TCK.

TRST

JTAG test reset with internal pulldown. TRST, when driven

high, gives the scan system control of the operations of the

device. If this signal is driven low, the device operates in its

functional mode, and the test reset signals are ignored.

NOTE: TRST must be maintained low at all times during

normal device operation. An external pulldown resistor is

required on this pin. The value of this resistor should be based

on drive strength of the debugger pods applicable to the

design. A 2.2-kΩ or smaller resistor generally offers adequate

protection. The value of the resistor is application-specific. TI

recommends that each target board be validated for proper

operation of the debugger and the application. This pin has an

internal 50-ns (nominal) glitch filter.

INTERNAL VOLTAGE REGULATOR CONTROL

VREGENZ

119

Internal voltage regulator enable with internal pulldown. To

enable the 1.2-V VREG, pull low to VSS. To disable, pull high

to VDDIO.

ANALOG, DIGITAL, AND I/O POWER

VDD

1.2-V digital logic power pins. If the internal 1.2-V VREG is

used, place a decoupling capacitor near each VDD pin and

distribute 12 µF to 26 µF evenly across all VDD pins. If an

external supply is used, TI recommends a minimum total

capacitance of 20 µF. The exact value of the decoupling

capacitance should be determined by your system voltage

regulation solution.

117

126

137

153

158

169

–

VDD3VFL

3.3-V Flash power pin. Place a minimum 0.1-µF decoupling

capacitor on each pin.

VDDA

3.3-V analog power pins. Place a minimum 2.2-µF decoupling

capacitor to VSSA on each pin.

–

www.ti.com

TMS320F28076, TMS320F28075

SPRS902J – OCTOBER 2014 – REVISED FEBRUARY 2021

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