TMS320F28076PZP datasheet(45/192 Pages) TI

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7.9.2 Reset Timing

XRS is the device reset pin. It functions as an input and open-drain output. The device has a built-in power-on

reset (POR). During power up, the POR circuit drives the XRS pin low. A watchdog or NMI watchdog reset also

drives the pin low. An external circuit may drive the pin to assert a device reset.

A resistor with a value from 2.2 kΩ to 10 kΩ should be placed between XRS and VDDIO. A capacitor should be

placed between XRS and VSS for noise filtering; the capacitance should be 100 nF or smaller. These values will

allow the watchdog to properly drive the XRS pin to VOL within 512 OSCCLK cycles when the watchdog reset is

asserted. Figure 7-4 shows the recommended reset circuit.

XRS

£100 nF

2.2 k

– 10 k

DDIO

Figure 7-4. Reset Circuit

7.9.2.1 Reset Sources

The following reset sources exist on this device: XRS, WDRS, NMIWDRS, SYSRS, SCCRESET, and

HIBRESET. See the Reset Signals table in the System Control chapter of the TMS320F2807x Microcontrollers

Technical Reference Manual .

The parameter th(boot-mode) must account for a reset initiated from any of these sources.

CAUTION

Some reset sources are internally driven by the device. Some of these sources will drive XRS low.

Use this to disable any other devices driving the boot pins. The SCCRESET and debugger reset

sources do not drive XRS; therefore, the pins used for boot mode should not be actively driven by

other devices in the system. The boot configuration has a provision for changing the boot pins in

OTP; for more details, see the TMS320F2807x Microcontrollers Technical Reference Manual .

7.9.2.2 Reset Electrical Data and Timing

Section 7.9.2.2.1 shows the reset ( XRS) timing requirements. Section 7.9.2.2.2 shows the reset ( XRS)

switching characteristics. Figure 7-5 shows the power-on reset. Figure 7-6 shows the warm reset.

7.9.2.2.1 Reset ( XRS) Timing Requirements

MIN

MAX

UNIT

th(boot-mode)

Hold time for boot-mode pins

1.5

tw(RSL2)

Pulse duration, XRS low on

warm reset

All cases

3.2

µs

Low-power modes used in

application and SYSCLKDIV > 16

3.2 * (SYSCLKDIV/16)

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TMS320F28076, TMS320F28075

SPRS902J – OCTOBER 2014 – REVISED FEBRUARY 2021

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