68HC705JB4 datasheet(101/134 Pages) FREESCALE

101 / 134 page

February 24, 1999

GENERAL RELEASE SPECIFICATION

MC68HC05JB4

ANALOG TO DIGITAL CONVERTER

MOTOROLA

REV 2

11-3

11.2

ADC STATUS AND CONTROL REGISTER (ADSCR)

The ADSCR is a read/write register containing status and control bits for the ADC.

Figure 11-2. A/D Status and Control Register

COCO — COnversion COmplete

1 =

An ADC conversion has completed; ADC Data Register ($0F)

contains valid conversion result.

0 =

ADC conversion not completed.

This read-only status bit is set when a conversion is completed, indicating that

the ADC Data Register contains a valid result. This COCO bit is cleared either

by a write to the ADSCR or a read of the ADC Data Register. Once the COCO

bit is cleared, a new conversion automatically starts. If the COCO bit is not

cleared, conversions are initiated every 32 cycles. In this continuous conver-

sion mode the ADC Data Register is refreshed with new data, every 32 cycles,

and the COCO bit remains set.

ADRC — ADC RC Oscillator Control

1 =

ADC uses RC oscillator as clock source.

0 =

ADC uses internal processor clock as clock source.

The RC oscillator option must be used if the internal processor is running below

1MHz. A stabilization time of typically 1ms is required when switching to the RC

oscillator option.

ADON — ADC On

1 =

ADC is switched ON.

0 =

ADC is switched OFF.

When the ADC is turned from OFF to ON, it requires a time tADON for the cur-

rent sources to stabilize. During this time ADC conversion results may be inac-

curate. Switching the ADC off disables the internal charge pump and RC

oscillator (if selected by ADRC=1), and hence saving power.

CH3:CH0 — Channel Select Bits

These four bits selects one of ten ADC channels for the conversion. Channels 0

to 5 correspond to inputs AD0-AD5 on port pins PC0-PC3, PB3 and PB4

respectively. Channels 12 and 13 are the ADC reference inputs VRH and VRL,

on port pins PC4 and PC5 respectively. Channels 14 and 15 are used for inter-

nal reference points. Table 11-1 shows the signals selected by the channel

select bits.

BIT 7

BIT 6

BIT 5

BIT 4

BIT 3

BIT 2

BIT 1

BIT 0

ADSCR

COCO

ADRC

ADON

CH3

CH2

CH1

CH0

$000E

reset:

00000000

Freescale Semiconductor, Inc.

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