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68HC705JB4 Datasheet(PDF) 103 Page - Freescale Semiconductor, Inc |
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68HC705JB4 Datasheet(HTML) 103 Page - Freescale Semiconductor, Inc |
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103 / 134 page ![]() February 24, 1999 GENERAL RELEASE SPECIFICATION MC68HC05JB4 ANALOG TO DIGITAL CONVERTER MOTOROLA REV 2 11-5 11.4 ADC DURING LOW POWER MODES The ADC continues normal operation in WAIT mode. To reduce power consump- tion in WAIT mode, the ADON and ADRC bits in the ADSCR should be cleared if the ADC is not used. If the ADC is in use and the internal bus clock is above 1MHz, it is recommended that the ADRC bit be cleared. In STOP mode, the ADC stops operation. Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com |
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