 |
Electronic Components Datasheet Search |
|
|
Electronic Components Datasheet Search |
|
DSPIC33EP128GS708 Datasheet(PDF) 196 Page - Microchip Technology |
|
|
|||||||||||||||||||||||||||||
DSPIC33EP128GS708 Datasheet(HTML) 196 Page - Microchip Technology |
|
|
196 / 484 page  dsPIC33EPXXXGS70X/80X FAMILY DS70005258C-page 196 2016-2018 Microchip Technology Inc. REGISTER 16-5: STCON: PWM SECONDARY MASTER TIME BASE CONTROL REGISTER U-0 U-0 U-0 HSC/R-0 R/W-0 R/W-0 R/W-0 R/W-0 — — — SESTAT SEIEN EIPU(1) SYNCPOL SYNCOEN bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 SYNCEN SYNCSRC2 SYNCSRC1 SYNCSRC0 SEVTPS3 SEVTPS2 SEVTPS1 SEVTPS0 bit 7 bit 0 Legend: HSC = Hardware Settable/Clearable bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-13 Unimplemented: Read as ‘0’ bit 12 SESTAT: Special Event Interrupt Status bit 1 = Secondary special event interrupt is pending 0 = Secondary special event interrupt is not pending bit 11 SEIEN: Special Event Interrupt Enable bit 1 = Secondary special event interrupt is enabled 0 = Secondary special event interrupt is disabled bit 10 EIPU: Enable Immediate Period Updates bit(1) 1 = Active Secondary Period register is updated immediately 0 = Active Secondary Period register updates occur on PWMx cycle boundaries bit 9 SYNCPOL: Synchronize Input and Output Polarity bit 1 = SYNCIx/SYNCO2 polarity is inverted (active-low) 0 = SYNCIx/SYNCO2 polarity is active-high bit 8 SYNCOEN: Secondary Master Time Base Synchronization Enable bit 1 = SYNCO2 output is enabled 0 = SYNCO2 output is disabled bit 7 SYNCEN: External Secondary Master Time Base Synchronization Enable bit 1 = External synchronization of secondary time base is enabled 0 = External synchronization of secondary time base is disabled bit 6-4 SYNCSRC<2:0>: Secondary Time Base Sync Source Selection bits 111 = Reserved 101 = Reserved 100 = Reserved 011 = PTG Trigger Output 17 010 = PTG Trigger Output 16 001 = SYNCI2 000 = SYNCI1 bit 3-0 SEVTPS<3:0>: PWMx Secondary Special Event Trigger Output Postscaler Select bits 1111 = 1:16 postcaler 0001 = 1:2 postcaler • • • 0000 = 1:1 postscaler Note 1: This bit only applies to the secondary master time base period. |
|
Link URL |
| Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Contact us | Privacy Policy | Link to Datasheet | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
English ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
