DSPIC33EP128GS708 datasheet(194/484 Pages) MICROCHIP

194 / 484 page

dsPIC33EPXXXGS70X/80X FAMILY

DS70005258C-page 194

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bit 3-0

SEVTPS<3:0>: PWM Special Event Trigger Output Postscaler Select bits(1)

1111 = 1:16 postscaler generates a Special Event Trigger on every sixteenth compare match event

•

0001 = 1:2 postscaler generates a Special Event Trigger on every second compare match event

0000 = 1:1 postscaler generates a Special Event Trigger on every compare match event

PTCON: PWM TIME BASE CONTROL REGISTER (CONTINUED)

Note 1: These bits should be changed only when PTEN = 0. In addition, when using the SYNCIx feature, the user

application must program the Period register with a value that is slightly larger than the expected period of

the external synchronization input signal.

PTCON2: PWM CLOCK DIVIDER SELECT REGISTER

U-0

—

bit 15

bit 8

U-0

R/W-0

—

PCLKDIV<2:0>(1)

bit 7

bit 0

Legend:

R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’

-n = Value at POR

‘1’ = Bit is set

‘0’ = Bit is cleared

x = Bit is unknown

bit 15-3

Unimplemented: Read as ‘0’

bit 2-0

PCLKDIV<2:0>: PWMx Input Clock Prescaler (Divider) Select bits(1)

111 = Reserved

110 = Divide-by-64, maximum PWM timing resolution

101 = Divide-by-32, maximum PWM timing resolution

100 = Divide-by-16, maximum PWM timing resolution

011 = Divide-by-8, maximum PWM timing resolution

010 = Divide-by-4, maximum PWM timing resolution

001 = Divide-by-2, maximum PWM timing resolution

000 = Divide-by-1, maximum PWM timing resolution (power-on default)

Note 1: These bits should be changed only when PTEN = 0. Changing the clock selection during operation will

yield unpredictable results.

DSPIC33EP128GS708 Datasheet(PDF) 194 Page - Microchip Technology

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